ADLINK DAQ/DAQE/PXI-20xx series multifunctional synchronous acquisition card

ADLINK DAQ/DAQE/PXI-20xx series multifunctional synchronous acquisition card

Product Overview

Core hardware features

The entire system has 4 synchronous differential analog inputs, integrated AI analog acquisition, AO waveform output, 24 DIO channels, 2 16 bit timers, multiple triggers, SSI multi card synchronization, hardware self calibration, and 32-bit plug and play PCI bus.

Three core performance distinctions:

Model ADC Resolution Maximum Synchronous Sampling AI FIFO

2010 14 bit code free 2MS/s 8K sampling points

2005 16 bit code free 500KS/s 512 sampling points

2006 16 bit code free 250KS/s 512 sampling points

General configuration:

Programmable gain x 1/x 2/x 4/x 8; Single/Bipolar Voltage Range (± 10/± 5/± 2.5/± 1.25V, 0~10/0~5/0~2.5/0~1.25V)

4 types of trigger sources: software trigger, external digital trigger, external analog trigger, SSI synchronous trigger

4 types of acquisition timing: pre trigger, mid trigger, post trigger, delayed trigger; Support for re triggering

Data transmission: software polling+PCI bus master DMA (distributed/aggregated chain DMA, breaking through continuous memory limitations)

AO: 2-channel 12 bit waveform output, maximum update rate 1MS/s, 2K point output FIFO

Synchronous digital input SDI (2010 only): 8 digital signals synchronized with AI to latch in sampled data

SSI system synchronous bus: Multi card cascaded synchronous clock, trigger, and conversion signals, PXI version multiplexed backplane trigger bus does not require additional cables

Full board without jumper design, all parameter software configuration, built-in hardware automatic calibration

Typical application scenarios

Automotive power/component testing, cable withstand voltage testing, transient impact signal acquisition, automated ATE testing bench, laboratory measurement, biomedical signal acquisition, multi-channel synchronous excitation response testing.

Detailed electrical specifications

(1) Simulate input AI

Input impedance 1G Ω/100pF, common mode voltage ± 11V; power on withstand ± 30V overvoltage, power-off ± 15V;

The maximum common mode rejection ratio (CMRR) of DC~60Hz is 97dB, and the differential anti-interference is extremely strong;

Built in 40MHz reference time base, external clock supports 1-40MHz TTL input;

Provide a complete parameter table for the full range -3dB small signal bandwidth, system noise LSB, and offset/gain error.

(2) Simulate output AO

Output ± 5mA driver, output impedance 0.3 Ω, short circuit protection; Establishment time 3 μ s (0.5LSB accuracy), slew rate 20V/μ s;

Internal 10V reference/external AOEXTREF dual reference optional, supporting AM amplitude modulation waveform output; The default output is 0V when powered on.

(3) Digital IO (82C55 chip)

24 channels of TTL/CMOS programmable IO, divided into A/B/C ports, each port has 4 high and low bits that can be independently set for input/output; Power on full high impedance input; In 2010, an additional 8 synchronized SDIs were captured synchronously with AI sampling.

(4) Universal Timer GPTC

2-channel 16 bit up/down counter, 8 working modes (pulse counting, cycle/pulse width measurement, single/continuous pulse generation, gate triggering, etc.), clock up to 10MHz.

(5) Environment and power consumption

Working temperature: 0-55 ℃, storage: -20~80 ℃, humidity: 10%~90%, no condensation;

PCI size 175 × 107mm, PXI standard 3U size; Main interface 68 pin VHDCI;

Power supply: 2005 with the highest power consumption 2.04A@5V In 2010/2006, it was 1.82A@5V .

Complete software stack (MAPS platform)

Linghua MAP (Measurement Automation Platform) unified driver ecosystem, fully supported by Windows, with three major development kits:

MAPS Core (essential underlying layer)

ACE (ADLINK Connection Explorer) Device Manager: Identify cards, configure DMA buffers, customize device aliases;

Built in SoftFrontPanel visualization software panel, real-time drawing of AI/AO waveforms, IO status, and counter values, without the need for programming or debugging of the acquisition card.

MAPS/C: C/C++Development SDK, header files API、 Complete example program.

MAPS/LV: LabVIEW dedicated VI library, supporting routines, suitable for automated testing and development.

Authorization mechanism: Unauthorized users can enjoy a free 2-hour commercial trial, while formal use requires the purchase of an authorization code.

Hardware installation

Packing List

Collecting card body, user manual, software installation guide; Cables and terminal boards are optional.

Mandatory anti-static requirements

Full process anti-static wristband+anti-static pad; Static electricity can easily damage ADC/FPGA chips. After unpacking, place the component face up and do not touch gold fingers with bare hands.

Board hardware layout

PCI version: 68 pin VHDCI main IO port, 20 pin SSI synchronous ribbon interface;

PXI version: 68 pin VHDCI, backplane PXI J2 multiplexed SSI synchronization signal, no external synchronization cable required;

Dial/jumper settings (only two hardware configurations)

SW1 4-digit DIP dip code: Board ID (0~15)

The multi card system distinguishes device numbers, and the driver tool needs to cancel "ignore ID" to take effect. The default is all OFF (ID0).

JP4 jumper: DIO pull-down enabled

Default conduction, power on DIO and pull down to low level; If disconnected, there will be no pull-down and high resistance state.

PCI plug and play configuration

IRQ、 Base address and DMA are automatically allocated by BIOS, without the need for manual jumpers; Troubleshooting BIOS slot interrupt settings for device conflicts.

Signal wiring specifications

Definition of connector pins

68 pin VHDCI main interface: includes 4 differential AI, 2 AO, 24 DIO, GPTC clock/gate control, external analog/digital trigger, AFI auxiliary timing input, SDI synchronous digital input (2010 only);

20 pin SSI synchronization interface (PCI): 7-channel global synchronization timing (time base, AD conversion, scan trigger, DA waveform trigger, etc.);

PXI Backplane J2: Maps SSI signals to the PXI trigger bus, eliminating the need for ribbon cables for multi card synchronization.

Two wiring schemes for analog input

Single ended input: The negative pole of the signal is uniformly connected to AIGND, with simple wiring but poor anti-interference ability, only used in short distance low-noise scenarios;

Differential input (recommended): Suitable for ground and floating sources (thermocouples, isolation sensors); Floating ground sources require the addition of bias resistors to provide a return path and significantly suppress common mode noise.

Core working principle

Principle of A/D analog acquisition

Data encoding format

2010: 14 bit binary complement, low 2 bits multiplexed SDI synchronous digital signal;

2005/2006: Pure 16 bit binary encoding without synchronous digital bits;

The manual provides a full-scale single/bipolar voltage digital code comparison table.

Two collection startup methods

Software single polling: single channel single point reading, timing controlled by software, suitable for low-speed measurement;

Programmable scanning acquisition (recommended for high speed): The sampling period is precisely controlled by a 24 bit SI scanning interval counter and PSC post sampling counter, based on a 40MHz hardware time base, with a sampling accuracy of nanoseconds.

Four major triggering modes timing sequence

Pre trigger: Continuous sampling is performed first, and only M sets of data before triggering are retained to capture the pre waveform of faults/impacts; Support M-enable to block early triggers and ensure complete M-point data.

Middle trigger: Simultaneously save the M-scan before triggering and the N-scan after triggering, and record the complete waveform before and after transient events.

Post trigger: Collection begins only after triggering, with regular steady-state signal measurement; Support for re triggering and segmented storage of multiple events.

Delay trigger: After triggering, wait for the specified clock cycle before starting the acquisition, and adapt to the delayed response of the tested object.

DMA high-speed transfer mechanism

Support distributed/clustered chain DMA: No need for the operating system to allocate large contiguous memory, the fragmented memory chain is directly transferred to the PCI control hardware for data transfer, with zero CPU intervention and maximum bandwidth utilization; Non chain maximum 8MB single transmission, chain unlimited, suitable for long-term continuous high-speed acquisition.

Principle of D/A waveform output

Two output modes

Real time software update: set a fixed voltage at a time;

Timed waveform generation: Generate continuous waveforms based on UI update interval, UC single point count, IC iteration count, DLY1 trigger delay, and DLY2 waveform interval with 5 sets of counters.

Waveform control function: limited/infinite iteration, trigger delay, multiple triggers; Provide three software stop modes (immediate stop, single waveform end stop, specified iteration cycle end stop).

Digital code and output voltage mapping: Distinguish between internal 10V reference single/bipolar output comparison table, support external reference to achieve custom output amplitude.

Digital IO and Synchronous SDI

The 24 channel 82C55 port can be configured with input and output in 4-bit increments; 2010 unique 8-channel SDI, synchronized with AI conversion edge locking, fully aligned with analog and digital timing, suitable for synchronous acquisition of switch values and voltage signals.

8 working modes of universal timer

Hardware independent 16 bit counter, covering commonly used industrial measurement/pulse scenarios: gate control counting, cycle measurement, pulse width measurement, single/continuous trigger pulse output, gate control continuous pulse, etc. Clock, gate control, addition and subtraction direction are all software programmable.

Trigger the complete architecture of the system

(1) Simulate triggering

Support 5 threshold determination logics: below lower limit, above upper limit, within interval, high latency, low latency; 8-bit programmable threshold level, suitable for oscillation, peak, and threshold monitoring scenarios.

(2) Digital trigger

EXTDTRIG (AI specific) and EXTWFTRIG (AO specific) are two independent TTL triggers, with selectable rising/falling edges and a minimum pulse width of 20ns.

Global timing and SSI multi card synchronization

AFI auxiliary timing input: external clock, external conversion/scan trigger signal replaces onboard internal time base;

SSI master-slave synchronization architecture: single host outputs time base/trigger, up to 3 slave cards synchronously collect data, multi-channel expansion without phase offset; The PXI model reuses the backplane trigger bus without the need for synchronous wiring.

Automatic calibration

Calibration storage structure: onboard EEPROM, 1 set of factory calibration area+3 sets of user-defined calibration areas, capable of storing calibration parameters under different temperature fields; Automatically load TrimDAC to correct offset and gain errors when powered on.

Automatic calibration process: No external standard source required, relying on onboard high-precision internal reference at 5ppm/℃; Preheat for 15 minutes before use, disconnect external cables to avoid load interference.

Calibration Save: After self calibration is completed, parameters can be written to any user partition, recording calibration time and ambient temperature, and quickly switching calibration configurations for multiple operating conditions.

Safety regulations

Hardware safety taboos: prohibit live plugging, liquid contact, and overpressure input; Lithium batteries can only be replaced with models of the same specifications to prevent explosions; Operations in high-temperature areas require waiting for cooling.

Fault repair: Only authorized Linghua engineers can disassemble it. Damage caused by water ingress, static electricity, and overvoltage is not covered by the warranty.