ADLINK DAQ/DAQE/PXI-250x series multifunctional analog output acquisition card

ADLINK DAQ/DAQE/PXI-250x series multifunctional analog output acquisition card

Product Overview and Hardware Specifications

1.1 Core Differences between Two Models

Model Analog Output AO Analog Input AI AO FIFO AI FIFO

2501 4-channel 12 bit 8-channel single ended 14 bit 8K point 2K point

2502 8-channel 12 bit (divided into A/B groups with 4 synchronized channels each) 4-channel single ended 14 bit 16K point 2K point

1.2 Core Hardware Function Modules

(1) Analog input AI (14 bit LTC1416 ADC, up to 400KS/s)

Range: Bipolar ± 10V, unipolar 0-10V, ± 35V continuous overvoltage protection, input impedance 1G Ω;

Storage: 2K hardware FIFO; Support four collection modes: pre/post/delayed/re triggered;

Transmission method: software single point polling, PCI main distributed DMA (high-speed without CPU occupation);

Timing: 40MHz built-in time base, can be connected to external clocks of 1-40MHz, multi-channel programmable scanning timing.

(2) Analog output AO (12 bit AD7945 DAC, maximum 1MS/s update rate, product core)

Grouping architecture: 2502 is divided into two groups, A and B, each with 4 DAC channels. The same group channel synchronously outputs without phase difference; 2501 Only Group A with 4 routes;

Reference source: Each group can independently select onboard 10V internal reference/external ± 510V reference, with built-in external reference compensation circuit;

Output characteristics: slew rate 20V/μ s, establishment time 2 μ s (± 10V full step), short circuit protection, maximum output current ± 5mA; default 0V when powered on;

Cache: 2501 8K point FIFO, 2502 16K point FIFO; Support hardware waveform generator, combined with multi-level counters to achieve complex waveforms.

(3) Universal Digital IO DIO

24 channel 82C55 programmable TTL port (PA/PB/PC three ports, high and low 4 bits can be independently set for input/output); Power on all high impedance inputs, JP4 jumper controls 1K pull-down enable (default power on low level).

(4) Dual channel 16 bit universal timer GPTC

2 independent up/down counters, up to 10MHz internal/external clock, 8 standard operating modes: gate counting, cycle measurement, pulse width measurement, single/continuous/re triggered pulse generation; Support software/hardware direction control and programmable signal polarity.

(5) SSI Multi Card Synchronous Bus

20 pin bidirectional synchronous interface, 7 global timing signals (time base, AD conversion, DA update, scan trigger, etc.); The PXI model can be mapped to the chassis J2 PXI trigger bus, achieving complete synchronization of multiple DAQ clocks/triggers.

1.3 Trigger complete system (AI, AO share trigger source)

Four types of trigger sources: software trigger, external digital trigger EXTWFTRIG, external analog trigger EXTATRIG, SSI bus synchronous trigger;

Simulate triggering with 5 criteria: below threshold, above threshold, within interval, high hysteresis, low hysteresis, 8-bit adjustable trigger level, programmable hysteresis voltage;

AI collection trigger: post trigger, delayed trigger, with heavy trigger/delayed trigger;

AO waveform triggering: equipped with 6 sets of timing counters, supporting limited/infinite iteration, segmented waveform, and interval delay output; Three stopping modes (immediate stop, complete current waveform stop, complete all iterations stop).

1.4 Electrical, Physical, and Environmental Parameters

Interface: Dual 68 pin VHDCI CN1/CN2 connector;

Power supply:+5V, typical 1.6A;

Size: Standard PCI 175 × 107mm, PXI is a 3U compact chassis version;

Working temperature range: 0-55 ℃, storage -20~70 ℃, humidity 10%~90%, no condensation;

Benchmark: Onboard 5V high-precision calibration source, temperature drift ± 2ppm/℃, long-term stability 6ppm/kWh. It is recommended to preheat for 15 minutes before calibration.

1.5 MAPS complete software ecosystem (unified driver framework)

MAPS Core (mandatory bottom layer)

ACE Connection Manager: Automatically identify cards, configure DMA memory, customize device aliases; Built in Soft Front Panel visualization software panel, which can manually control AI acquisition, AO waveform output DIO、 Counter, real-time graphical observation waveform; Equipped with chassis monitoring and hardware self-test tools.

MAPS/C：Windows C/C++ SDK， Head files, complete set of APIs, and engineering examples;

MAPS/LV: LabVIEW dedicated VI library, containing a large number of waveform generation/acquisition routines;

MAPS/C #:. NET C # Development Kit (documentation to be released);

Authorization mechanism: Without authorization, only a 2-hour trial is allowed. For commercial use, an official authorization code must be purchased.

Hardware Installation, Dialing and Jumping

2.1 Packaging and anti-static specifications

The packaging contains a collection card, a paper manual, and a software installation guide; The board is an electrostatic sensitive device, and it must be disassembled with a grounded anti-static wristband and anti-static pad, only holding the edge of the board; Before powering on, check that the socket IC is not loose or damaged. It is strictly prohibited to turn on the power.

2.2 Differentiation of Board Hardware Layout

DAQ standard PCI: sub motherboard architecture, front dual 68 pin CN1/CN2, side SSI synchronous socket;

PXI-250x: 3U chassis version, front locking buckle, SSI signal multiplexing chassis J2 trigger bus;

DACe PCIe: The mother board to board connector transmits signals, and the interface layout is the same as standard PCI.

2.3 Hardware configuration (no IRQ/base jumper, fully PnP software allocation)

SW1 4-digit DIP dialing: Set board ID (0~15) to distinguish devices in multi card systems; The driver tool defaults to ignoring IDs and needs to manually uncheck and enable them;

JP4 jumper: DIO power on pull-down resistor switch, short circuit=IO initial low, disconnect=power on high resistance;

2.4 PCI Plug and Play Mechanism

BIOS automatically assigns IRQ, IO addresses, and DMA channels without the need for hardware jumpers; The faults are mostly interrupt conflicts, and it is necessary to enter BIOS to adjust PCI resource allocation.

Definition of Connector Pins (CN1+CN2+SSI)

3.1 CN1/CN2 68 pin hybrid interface

AO channels: AO0~AO3 (Group A), AO4~AO7 (Group B, only 2502), with each group independently referencing AOEXTREF externally;

AI channel: AI0~AI3 (2502)/AI0~AI7 (2501), EXTATRIG external analog trigger multiplexed AI pin;

GPTC signal: Two counters CLK, GATE, UPDOWN, OUT;

DIO port: PA/PB/PC all 24 digital IO channels;

Auxiliary pins: AFI0/AFI1 external timing input, AO_TRIG-OUT waveform synchronous output, EXTWFTRIG external digital waveform trigger, analog ground AGND, digital ground DGND,+5V auxiliary power supply.

3.2 SSI synchronous 20 pin interface

7-way bidirectional global timing bus: SSI_TIMEBASE (main time base) SSI_ADCONV、SSI_DAWR、SSI_SCAN_START、AD_TRIG、DA_TRIG； The PXI models can be mapped to the J2 PXI Trigger0-6 chassis one by one, achieving multi card synchronous acquisition/waveform output.

Basic Working Principle

4.1 A/D Analog Acquisition Principle

Data format: 14 bit binary complement, distinguishing the numerical encoding table corresponding to single/bipolar ranges;

Two collection modes:

Software polling: single conversion, low-speed single point measurement, timing controlled by the program;

Programmable hardware scanning (recommended): 4 sets of 24 bit hardware counters (SI scan cycle, SI2 channel interval, PSC single trigger total scan count, Delay trigger delay), constraining SI ≥ SI2 x single scan channel count;

Three major AI triggering timings (complete timing diagram attached):

Post trigger: Start scanning a fixed number of times after triggering;

Delay trigger: trigger to wait for programmable delay before collecting;

Re triggered: Multiple external triggers can be cyclically collected;

Scattered DMA transfer: Supports non contiguous memory chain descriptors, no upper limit for single acquisition length, zero CPU load for high-speed acquisition, and the only transfer method that supports pre/delay triggering.

4.2 D/A waveform generation (core product function)

Hardware group synchronization mechanism: Four DACs in the same group share the update timing, output without phase offset, suitable for multi-channel synchronous waveforms (orthogonal signals, multi-channel excitation);

Generate 6 sets of timing counters for waveform generation:

UI: Single channel update interval; UC: Total number of points in a single waveform; IC: number of waveform iterations;

DLY1: Trigger pre delay; DLY2: waveform interval delay; Trig: Maximum count that can be triggered again;

Three waveform stop modes:

Mode 1: Immediately interrupt output upon receiving a stop signal;

Mode 2: Stop after completing the current complete waveform;

Mode 3: Stop after completing all set iterations;

Waveform expansion capability: standard sine/triangle/sawtooth waves, arbitrary custom waveforms, amplitude modulation AM (external reference modulation), frequency modulation FM (external clock controlled update rate), segmented waveforms, intermittent iterative waveforms; Supports infinite loop output.

4.3 24 channel digital IO

82C55 standard programmable IO architecture, A/B/C ports are independently configured, and the C port has 4 high and low bits that can be split for input and output; No hardware latch, only software read-write level.

4.4 GPTC 8 working modes of counters

Complete coverage of commonly used industrial counting requirements:

Gate control event counting; 2. Single cycle measurement; 3. Single pulse width measurement;

Gate controlled single pulse; 5. Trigger a single pulse; 6. Can trigger a single pulse again;

Single trigger continuous pulse; 8. Gate controlled continuous periodic pulse;

Real time reading of count values during operation without interrupting the counting process.

4.5 Triggering and Global Temporal Routing

Simulate triggering dual input sources: external EXTATRIG pin, any AI acquisition channel, 5 threshold judgment logics;

Global timing routing: The internal 40MHz time base, AFI external timing, and SSI synchronization bus signals can be switched to each other, serving as AI/DA/GPTC clock sources to achieve multi device timing synchronization.

Automatic Calibration Function

Onboard EEPROM stores calibration parameters: 1 set of factory default calibration area+3 sets of user-defined calibration storage areas, which can save calibration constants in multiple environments and load them directly on site when switching;

Auto Cal automatic calibration: No need for external standard sources, one click calibration of AI gain/offset, DAC gain/offset;

Calibration standard: Preheat for 15 minutes after startup, disconnect external wiring before calibration to avoid load interference with accuracy; It is recommended to recalibrate regularly for long-term use to offset temperature drift and component aging errors.

Equipment safety requirements

Disassembly, assembly, and calibration must be carried out with the entire machine powered off;

Avoid liquid and high-temperature sealed environments, and do not touch the heating area on the board directly;

Built in backup lithium battery, there is a risk of explosion when replacing the wrong model, and the waste battery is recycled in compliance with regulations;

Only authorized engineers are authorized to disassemble and repair the machine, and unauthorized disassembly will result in loss of warranty.