ADLINK PXIe-9834 4-channel 16 bit, up to 80MS/s synchronous sampling PXIe digitizer

ADLINK PXIe-9834 4-channel 16 bit, up to 80MS/s synchronous sampling PXIe digitizer

Product Overview and Core Features

Analog acquisition: 4-channel single ended synchronous 16 bit ADC; The highest sampling rate is 80MS/s, and the frequency can be divided as low as about 1.22kS/s; Simulate bandwidth of 3dB up to 40MHz.

Input configuration: The software can choose AC/DC coupling; Impedance can be switched between 50 Ω/1M Ω; Range: ± 0.5   V, ± 1   V, ± 5   V, ± 10   V (± 10V only supports 1M Ω impedance).

Digital filtering: Onboard can be configured with 10 MHz/20 MHz digital filters.

Clock system: internal 80MHz crystal oscillator; Support external sampling clock input; Support external 10MHz reference clock; Multi module synchronization can be achieved using the PXIe backplane PXI_CLK10 as a reference.

Storage and bus: 1GB onboard DDR3 memory; PCIe Gen1 x4； Support Scatter Gather DMA to achieve high-speed continuous streaming.

Onboard automatic calibration: Built in high-precision reference source, self calibration can be completed without external instruments; The calibration parameters are saved in the onboard EEPROM.

Front panel interface (all SMA)

CHO~CH3: 4-channel analog input;

CLK IN: External sampling clock/external 10MHz reference clock input;

TRG IN: External digital trigger input.

Typical Applications

Partial discharge detection, power equipment monitoring

Non destructive testing (NDT)

Radar, LiDAR signal acquisition

Key electrical specifications

Analog input

Item Parameter

Channel 4 single ended, 16 bit synchronous sampling

The maximum sampling rate is 80MS/s, and the minimum is around 1.22kS/s

Bandwidth (-3dB) 40 MHz

Input range: ± 0.5V, ± 1V, ± 5V, ± 10V (± 10V is only 1M Ω)

Input impedance software switch between 50 Ω/1M Ω

Coupling AC/DC software optional

Digital filtering 10MHz, 20MHz switchable

Overvoltage withstand 50 Ω mode, maximum 7Vrms; 1M Ω mode with a maximum ± 30V

Misalignment error of 0.8~8 mV (varying with range and impedance)

Maximum gain error ± 0.6%

The background noise of the system is 0.1~1.5 mVrms, and the larger the range, the higher the noise

Crosstalk DC -10MHz ± 0.5V ＜ -80dB; Other ranges<-90dB

Spectrum indicator (filter off) SINAD: 65-68dB; THD‑78dB； SFDR78dB； SNR65‑69dB

Time based clock

The accuracy of the internal oscillator is less than ± 25 ppm;

External sampling clock: 20-80 MHz, 50 Ω, AC coupling, 0.45~5Vpp, duty cycle 45-55%;

External reference clock: 10 MHz ± 2kHz, used for PLL phase locking to achieve multi card clock synchronization;

The PXIe backplane PXI_CLK10 can be directly used as a reference clock without the need for external wiring.

Trigger the system

Trigger sources: software trigger, external digital trigger (TRG IN SMA), 4-channel analog trigger, PXI Trigger Bus [0-7], PXI-STAR, PXIe-DSTARB (differential star trigger, slot skew<150ps).

External digital trigger: 3.3V TTL, 5V withstand voltage; Optional rising/falling edge; The minimum pulse width is 20 ns.

Five triggering working modes

Post Trigger: After the trigger arrives, collect the set point count;

Delayed Trigger: After receiving the trigger, wait for a programmable delay before starting data collection;

Pre Trigger: Save the sampling data before the triggering event;

Middle Trigger: Simultaneously collect data before and after triggering, with independent configuration of the number of points before and after triggering;

Re Trigger: Multiple triggering events, with each trigger collecting a set of waveforms that are automatically processed by hardware.

Hardware counter parameters

ScanIntrv (scan interval counter, 16 bit): Divides the 80MHz main clock to achieve a lower sampling rate;

DataCnt (31 bit data counter): the number of sample points collected in a single operation;

TribDelayTicks (16 bit delay counter): Clock beats triggered by delay;

ReTrgCnt (31 bit trigger counter): Set the acceptable number of triggers.

Mechanical, power consumption, environment

PCB size: 165   mm × 100   mm;

Power consumption: standby 5.46W, maximum 9.28W;

Working temperature range of 0-55 ℃, storage range of -20~80 ℃;

Certification: EN 55032, ANSI C63.4 Class B.

Software architecture MAPS (consistent with PXIe-9529H software stack)

Business drivers require authorization codes; Unauthorized access to 2-hour demo version.

MAPS Core (mandatory)

ACE (ADLINK Connection Explorer) Device Manager: Identify hardware, configure DMA buffers, set device aliases; Built in Soft Front Panel allows for direct GUI configuration of parameters, waveform acquisition, and FFT analysis.

PXI platform resource management ChassisWatch、 Module testing tool.

MAPS/C: C/C++development library, header files API、 Example.

MAPS/LV: LabVIEW Drivers and Examples.

DMA data transfer

PCIe‑Gen1 x4， Theoretical bandwidth of 640 MB/s;

Support for scattered clustered DMA: non contiguous memory linked list; Do not enable the maximum single transmission of 8MB for clustering; after enabling, it is only limited by the system's physical memory; Support circular multi buffering for continuous acquisition;

The data is first written into the onboard FIFO/1GB onboard memory, and then DMA transferred to the host memory.

Hardware installation

Electrostatic sensitive devices; Hot plugging is prohibited. The entire machine must be powered off for operation, and anti-static wristbands and pads must be worn.

Turn off the power of the PXIe chassis and unplug the power cord;

Align the module with the slot rail of the chassis and push it in. Tighten the pop-up handle and hear a "click". Tighten the panel screws;

On power, Windows recognizes hardware through MAPS Core.

Packing list: PXIe-9834 digitizer, quick start guide.

Multi module synchronization scheme

Four channels within a single module share the same clock and trigger, naturally synchronized; Multiple modules need to synchronize the trigger source and time base clock simultaneously, providing three synchronization methods:

External instrument synchronization: The external signal source outputs a unified clock and trigger, which are respectively connected to the CLK IN and TRG IN of each card; Require cables to be of equal length to reduce skewness.

Module master-slave cascade: The master card outputs clock and triggers CLK IN and TRG IN connected to the slave card, requiring signal buffering and cables of equal length.

PXIe backplane instrument signal (recommended, no external wiring required)

Clock synchronization: All slave cards use chassis PXI_CLK10 as PLL reference;

Trigger synchronization: The main card output triggers a certain PXI Trigger Bus/PXI_STAR/PXIe-DSTARB; Select the corresponding backplane signal from the trigger source of the card;

PXIe-DSTARB differential star trigger, with slot to slot timing skew less than 150ps, suitable for high-precision synchronization.

Appendix A Calibration Mechanism

The onboard EEPROM is divided into two storage areas:

Bank0 (factory area) write protection: Factory calibration constant, driver loaded by default, cannot be overwritten by automatic calibration;

Bank1 (User Area): Save the user's automatic calibration results.

Auto Calibration Automatic Calibration

No external standard source required, use onboard internal reference voltage source; Eliminate offset and gain errors, compensate for temperature drift;

Suggested operation: Preheat for at least 20 minutes when powered on, disconnect the external input cable, and then perform self calibration;

The software API can be set to load Bank0 or Bank1 upon startup and permanently store it in EEPROM.