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Home >> GE >> GE IS220PAICH1A Analog Input/Output: 10 analog inputs and 2 analog outputs
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GE IS220PAICH1A Analog Input/Output: 10 analog inputs and 2 analog outputs

From: | Author:Wang | Time :2024-12-18 | 248 visit: | Share:

GE IS220PAICH1A Analog Input/Output: 10 analog inputs and 2 analog outputs

The PMC PCI-X sites of the V7769 connect Standard PCI Interrupt Lines to the
PCI-E to PCI-X bridge as shown in Figure 2-1 on page 42. The PCI-E bridge (PLX
PEX8114) converts the PCI INTx interrupts into virtual PCI Express interrupts
that are signaled back to the chipset over the PCI Express Interface.
Interrupts on Peripheral Component Interconnect (PCI) Local Bus are defined as
“level sensitive,” asserted low (negative true), using open drain output drivers.
The assertion and de-assertion of an interrupt line, INTx#, is asynchronous. A
device asserts its INTx# line when requesting attention from its device driver.
Once the INTx# signal is asserted, it remains asserted until the device driver clears
the pending request. When the request is cleared, the device de-asserts its INTx#
signal.
PCI defines one interrupt line for a single function device and up to four interrupt
lines for a multifunction device or connector. For a single function device, only
INTA# may be used while the other three interrupt lines have no meaning.
Figure 2-1 on page 42 depicts the V7768/V7769 interrupt logic pertaining to FPGA
timer operations and the PCI expansion site.
Any function on a multifunction device can be connected to any of the INTx#
lines. The Interrupt Pin register defines which INTx# line the function uses to
request an interrupt. If a device implements a single INTx# line, it is called INTA#;
if it implements two lines, they are called INTA# and INTB#; and so forth. For a
multifunction device, all functions may use the same INTx# line, or each may
have its own (up to a maximum of four functions), or any combination thereof. A
single function can never generate an interrupt request on more than one INTx#
line.
The PIC accepts the PCI interrupts through lines that are defined by the BIOS.


Table 2-5 PCI Device Interrupt Mapping by the BIOS
Device Component Vendor ID Device ID ID Select PCI IRQ Arbitration
Request Line
PCI-to-VME Bridge Tundra Universe IID 0x10E3 0x0000 AD27 INTD REQ1
Timer/SRAM FPGA GE Proprietary 0x114A 0x0004 AD26 INTC N/A
PMC N/A N/A N/A AD24 INTA, B, C, D REQ0
Ethernet Controller Intel 82571EB 0x8086 0x105E N/A N/A N/A
PCI Host Bridge GMCH 0x8086 0x27A0 N/A N/A N/A
VGA Controller GMCH 0x8086 0x27A2 N/A N/A N/A
Integrated Graphics GMCH 0x8086 0x27A6 N/A N/A N/A
PCI-LPC Bridge ICH7-M 0x8086 0x27BD N/A N/A N/A
USB UHCI Controller ICH7-M 0x8086 0x27C8
0x27C9
0x27CA
0x27CB
N/A N/A N/A
USB EHCI ICH7-M 0x8086 0x27CC N/A N/A N/A
SMBus Controller ICH7-M 0x8086 0x27DA N/A N/A N/A
PCI-E Controller ICH7-M 0x8086 0x27D0 N/A N/A N/A
PCI-E Controller ICH7-M 0x8086 0x27E0 N/A N/A N/A
DMI-PCI Bridge ICH7-M 0x8086 0x2448 N/A N/A N/A
PCI-E Switch* PLX 8518 0x10B5 0x8518 N/A N/A N/A
PCI-E to PCI-X
Bridge*
PLX 8114 0x10B5 0x8114 N/A N/A N/A
LSI SAS Controller* LSI1064E 0x1000 0x0056 AD16 N/A N/A
PCI-E Graphics Port GMCH 0x8086 27A1 N/A N/A N/A
SATA Controller ICH7-M 0x8086 27C4 N/A N/A N/A
* Only available on V7769
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