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GE IS220PDIIH1A IS220PDIIH1B Isolated Contact Inputs: 16 discrete inputs

From: | Author:Wang | Time :2024-12-18 | 101 visit: | Share:

GE IS220PDIIH1A IS220PDIIH1B Isolated Contact Inputs: 16 discrete inputs

Table 2-2 V7768/V7769 I/O Address Map
I/O Address Range Size in
Bytes HW Device PC/AT Function
$000 - $00F 16 DMA Controller 1
$010 - $01F 16 Reserved
$020 - $021 2 Master Interrupt Controller
$022 - $03F 30 Reserved
$040 - $043 4 Programmable Timer
$044 - $05F 30 Reserved
$060 - $064 5 Keyboard, Speaker, System Configuration
$065 - $06F 11 Reserved
$070 - $071 2 Real-Time Clock
$072 - $07F 14 Reserved
$080 - $08F 16 DMA Page Registers
$090 - $091 2 Reserved
$092 1 Alt. Gate A20/Fast Reset Register
$093 - $09F 11 Reserved
$0A0 - $0A1 2 Slave Interrupt Controller
$0A2 - $0BF 30 Reserved
$0C0 - $0DF 32 DMA Controller 2
$0E0 - $16F 142 Reserved
$170 - $177 8 ICH7-M Secondary Hard Disk Controller
$178 - $1EF 120 User I/O
$1F0 - $1F7 8 ICH7-M Primary Hard Disk Controller
$1F8 - $277 128 User I/O
$278 - $27F 8 I/O Chip Reserved
$280 - $2E7 104 Reserved
$2E8 - $2EE 7 UART* COM4 Serial I/O*
$2EF - $2F7 9 User I/O
$2F8 - $2FE 7 Super I/O Chip COM2 Serial I/O (16550 Compatible)
$2FF - $36F 113 Reserved
$370 - $377 8 Super I/O Chip* Secondary Floppy Disk Controller*
$378 - $37F 8 Super I/O Chip Reserved
$380 - $3E7 108 Reserved
$3E8 - $3EE 7 UART* COM3 Serial I/O*
$3F0 - $3F7 8 Super I/O Chip* Primary Floppy Disk Controller*
$3F8 - $3FE 7 Super I/O Chip COM1 Serial I/O (16550 Compatible)
$3FF - $4FF 256 Reserved
$500 - $CFF 2048 Reserved
*While these I/O ports are reserved for the listed functions, they are not implemented on the V7768/
V7769. They are listed here to make the user aware of the standard PC usage of these ports.


In addition to an I/O port address, an I/O device has a separate hardware
interrupt line assignment. Assigned to each interrupt line is a corresponding
interrupt vector in the 256-vector interrupt table at $00000 to $003FF in memory.
The 16 maskable interrupts and the single Non-Maskable Interrupt (NMI) are
listed in Table 2-3 along with their functions. Table 2-4 on page 38 details the
vectors in the interrupt vector table. The interrupt number in HEX and decimal
are also defined for real and protected mode in Table 2-4 on page 38.
The interrupt hardware implementation on the V7768/V7769 is standard for
computers built around the PC architecture, which evolved from the IBM PC/XT.
In the IBM PC/XT computers, only eight interrupt request lines exist, numbered
from IRQ0 to IRQ7 at the Programmable Interrupt Controller (PIC). The IBM PC/
AT computer added eight more IRQx lines, numbered IRQ8 to IRQ15, by
cascading a second slave PIC into the original master PIC. IRQ2 at the master PIC
was committed as the cascade input from the slave PIC. This architecture is
represented in Figure 2-1 on page 42.
To maintain backward compatibility with PC/XT systems, IBM chose to use the
new IRQ9 input on the slave PIC to operate as the old IRQ2 interrupt line on the
PC/XT Expansion Bus. Thus, in AT systems, the IRQ9 interrupt line connects to
the old IRQ2 pin (pin B4) on the AT Expansion Bus (or ISA bus).
Table 2-3 Interrupt Line Assignments
IRQ AT Function Comments
NMI Parity Errors
(Must be enabled in BIOS Setup)
Used by V7768/V7769 PCI bus Interface
0 System Timer Set by BIOS Setup
1 Keyboard Set by BIOS Setup
2 Duplexed to IRQ9
3 COM2
4 COM1
5 Unused
6 Floppy Controller
7 Unused
8 Real-Time Clock
9 Old IRQ2 SVGA or Network I/O
10 Not Assigned Determined by BIOS
11 Not Assigned Determined by BIOS
12 Mouse
13 Math Coprocessor
14 AT Hard Drive
15 Flash Drive
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