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Home >> GE >> GE VMIVME-7700 Ultra Low Voltage Intel® Celeron® VMEbus
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GE VMIVME-7700 Ultra Low Voltage Intel® Celeron® VMEbus

From: | Author:Wang | Time :2024-12-18 | 124 visit: | Share:

GE VMIVME-7700 Ultra Low Voltage Intel® Celeron® VMEbus

• Comprehensive diagnostics

• Optional disabling of local boots
• Dual-boot option lets users select network or local booting
Serial Ports: Two 16550-compatible serial ports are featured on
the VMIVME-7750 front panel. The serial channel has a 16-b
FIFO to support baud rates up to 115 Kbaud. Requires two
micro-DB-9 to
yte
standard DB-9 adapters, GE Fanuc P/N 360-
ined
oard and mouse connector. A Y-adapter cable is
E
n option to allow the
n I/O space, and are completely
e a nonmaskable interrupt (NMI)
erved when
e
O connection to
tion
d configuration
gh performance PCI-to-VME interface from
ller.
rogrammed to provide the
arbitration:
GL)
Priority (PRI)
010050-001.
Keyboard and Mouse Ports: The VMIVME-7750 has a comb
PS/2 keyb
included.
Flash Memory: The VMIVME-7750 provides up to 1 Gbyte of IDE
CompactFlash memory accessible through the secondary ID
port. The VMIVME-7750 BIOS includes a
board to boot from the Flash memory.
Timers: The VMIVME-7750 provides the user with two 16-bit
timers and two 32-bit timers (in addition to system timers).
These timers are mapped i
software programmable.
Watchdog Timer: The VMIVME-7750 provides a software programmable watchdog timer. The watchdog timer is enabled
under software control. Once the watchdog timer is enabled,
software must access the timer within the specified timer period
or a timeout will occur. A user jumper allows the timeout to
cause a reset. Independent of the jumper, software can enable
the watchdog timeout to caus
or a VMEbus SYSFAIL.
Nonvolatile SRAM: The VMIVME-7750 provides 32 Kbyte of
nonvolatile SRAM. The contents of the SRAM are pres
+5V power is interrupted or removed from the unit.
PMC Expansion Site: The VMIVME-7750 supports IEEE P1386
common mezzanine card specification with a 5V PCI mezzanin
card (PMC) expansion site. The PMC site provides for standard
I/O out the VMEbus front panel. An optional I/
the VMEbus P2 connection can be provided.
Contact GE Fanuc Embedded Systems for more informa
concerning PMC modules and compatibility.
Universal Serial Bus (USB): The VMIVME-7750 provides a front
panel dual connection hub host controller for the USB.
Supported USB features include: isochronous data transfers,
asynchronous messaging, self-identification an
of peripherals, and dynamic (hot) attachment.
VMEbus Interface: The VMIVME-7750 VMEbus interface is based
on the Universe IIB hi
Newbridge/Tundra.
System Controller: The VMEbus system controller capabilities
allow the board to operate as a slot 1 controller, or it may be
disabled when another board is acting as the system contro
The system controller may be p
following modes of
Round Robin (RRS)
Single Level (S


The system controller provides a SYSCLK driver, IACK* daisychain driver, and a VMEbus access timeout timer. The system
controller also provides an arbitration timeout if BBSY* is not
seen within a specified period after a BGOUT* signal is issued.
This period is programmable for 16 or 256 µs.
VMEbus Requester: The microprocessor can request and gain
control of the bus using any of the VMEbus request lines (BR3*
to BR0*) under software control. The requester can be
programmed to operate in any of the following modes:
Release-On-Request (ROR)
Release-When-Done (RWD)
VMEbus Capture and Hold (BCAP)
Mailboxes: The VMEbus interface provides four 32-bit
mailboxes, which are accessible from both the microprocessor
and the VMEbus providing interprocessor communication. The
mailboxes have the ability to interrupt the microprocessor when
accessed by VMEbus.
Interrupt Handler: The interrupt handler monitors, and can be
programmed to respond to any or all VMEbus IRQ* lines. All
normal-process VMEbus-related interrupts can be mapped to
PCI INTA# or SERR# interrupts. These include:
Mailbox interrupts
VMEbus interrupts
VMEbus interrupter IACK cycle (acknowledgment of
VMIVME-7750 VMEbus-issued interrupts)
All error processing VMEbus-related interrupts can be mapped
to PCI INTA# or SERR#. Note: PCI SERR# initiates a SBC NMI.
These include:
ACFAIL* interrupt
BERR* interrupt
SYSFAIL* interrupt
The interrupt handler has a corresponding STATUS/ID register
for each IRQ* interrupt. Once the handler receives an IRQ*, it
requests the VMEbus and, once granted, it performs an IACK
cycle for that level. Once the IACK cycle is complete and the
STATUS/ID is stored in the corresponding ID register, an
appropriate interrupt status bit is set in an internal status
register, and a PCI interrupt is generated. The PCI interrupt can
be mapped to PCI INTA# or SERR#.
Interrupter: Interrupts can be issued under software control on
any or all of the seven VMEbus interrupt lines (IRQ7* to IRQ1*). A
common ID register is associated with all interrupt lines. During
the interrupt acknowledge cycle, the interrupter issues the ID to
the interrupt handler.
The interrupter can be programmed to generate a PCI INTA# or
SERR# interrupt when a VMEbus interrupt handler
acknowledges a software-generated VMEbus interrupt.
Byte Swapping: The Intel 80x86 family of processors use littleendian format. To accommodate other VMEbus modules that
transfer data in big-endian format such as the 680x0 processor
family, the VMIVME-7750 incorporates byte-swapping
hardware. This provides independent byte swapping for both
the master and slave interfaces. Both master and slave
interface byte swapping are under software control.
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