ADLINK PCI-7440 series (PCI-7442/7443/7444) high-density isolated digital I/O cards

ADLINK PCI-7440 series (PCI-7442/7443/7444) high-density isolated digital I/O cards

Comparison of Product Model Positioning and Core Specifications

This series consists of three PCI standard high-density isolated digital IO cards, all equipped with 1250VRMS optoelectronic isolation, 32 universal TTL bidirectional IO, hardware state change interrupt (COS), hardware watchdog WDT, and only differentiated by the number of isolated DI/DO channels:

Model Isolation DI Channel Isolation DO Channel Core Purpose

PCI-7442 64 channel 64 channel hybrid acquisition+control, universal for production lines

PCI-7443 128 channel 0-channel pure large quantity digital input, sensor batch acquisition

PCI-7444 0-channel 128 channel pure high-power digital output, batch driven relay/solenoid valve

General Hardware Core Features

Optoelectronic isolation protection: 1250VRMS isolation withstand voltage, DI non-polar input, suppresses industrial ground loop and surge interference;

Hardware COS interrupt: Any DI level jump (rising/falling edge) triggers a hardware interrupt, without the need for CPU polling, significantly reducing load;

Secure output mechanism (unique to 7442/7444)

Power on programmable DO default level (stored in onboard Flash);

Hot Reset Hold to maintain output state;

The watchdog automatically switches the safety output level when it exceeds the time limit to prevent the device from losing control;

Hardware watchdog WDT: 32-bit counter, 10MHz reference, timeout range 0~429.496 seconds, timeout triggers interrupt+safety DO;

32 channels of universal TTL IO: independent JP3/JP4 sockets, 4mA driver per channel, compatible with 3.3V/5V levels, can be separately configured for input/output by software;

Multi card recognition DIP dialing S1: 4-digit dialing setting for 0-15 card IDs, allowing for quick differentiation and addressing between multiple cards and the same host;

Electrical parameters

Isolation DI: Input 5~28V high level, 0~1.5V low level, input resistance 4.7k Ω;

Isolation DO: Open drain MOS output, maximum single channel 250mA, external 5-40V load;

Power consumption: 7442/7444 typical+5V 800mA; 7443 typical+5V 550mA;

Environmental indicators: working temperature of 0-60 ℃, storage temperature of -40~80 ℃, humidity of 5%~85%, no condensation; The standard PCI size is 174.7 × 106.7mm.

Hardware layout, interface and pin definition

1. Overall interface distribution of the board

The front of all three boards includes:

Two 68 pin SCSI isolated IO main interfaces, CN1 and CN2:

PCI-7442：CN1=0~63 DI，CN2=0~63 DO；

PCI-7443：CN1=0~63 DI，CN2=64~127 DI；

PCI-7444：CN1=0~63 DO，CN2=64~127 DO；

JP3 and JP4 20 pin TTL sub interfaces: JP3 corresponds to TTL0~15, JP4 corresponds to TTL16~31;

S1 four level DIP dialing: board ID configuration;

PCI 32-bit Gold Finger Bus.

2. Key interface pin rules

Isolation of DI common end COM: Every 8 DI channels share a set of COM common ground, which facilitates grouping and external sensor power supply;

Isolation of DO Public VDD: Every 8 channels of DO provide a set of external load power supply pins IGND, suitable for relay and inductive load freewheeling; Onboard 5V auxiliary power supply (maximum 100mA);

TTL IO: Every 16 channels are equipped with a set of SGND signals, and the software switches input and output channels by channel;

The complete appendix provides all pin function definitions for CN1/CN2/JP3/JP4, distinguishing channel numbers, common power supplies, and empty pin N/C.

Core Circuit and Working Principle

Isolated digital input circuit

Adopting PC3H4 optocoupler isolation chip, built-in bidirectional protection diode, supporting positive/negative non-polar voltage input; External series current limiting resistor, 33MHz sampling clock captures level jumps, and can capture a minimum of 31ns narrow pulse.

COS state change interrupt mechanism

DI is divided into independent CPLD control units in groups of 32 channels: 7442 with two sets of CPLDs and 7443 with four sets of CPLDs;

Each DI group can individually turn on/off COS interrupts; The level jump automatically locks the current DI state to the register;

Before clearing the interrupt, it will not receive new jumps and supports software to read the interrupt group and specific channel, eliminating the need for full channel polling.

Isolated digital output circuit (7442/7444)

The ADuM isolation chip isolates the PCI control side from the external power side, with MOS transistor open drain output; Inductive loads (relays, coils) require external current diodes, and the VDD pin provides an external power supply circuit; Support batch synchronous output and batch read back of current output level.

Watchdog WDT safety logic

Software timed reload counter, timeout triggers hardware interrupt;

After activating the Safety Out function, WDT overflow automatically loads the preset safety DO level in Flash;

Combined with hot reset hold function: The system's soft restart does not cut off the output of external actuators, avoiding production line misoperation.

Universal TTL IO

Independent 32 bidirectional channels, without optoelectronic isolation, only used for low-voltage signal interaction inside the board and cabinet, with limited driving capacity per channel (4mA).

Complete description of underlying registers

All registers are 16 bits and only support 16 bit IO read and write. They are addressed with PCI base address BASE offset and divided into four major register groups:

1. Isolate DI registers (7442/7443)

DI Read Register: Store the current input level in groups of 32 channels;

COS Enable Register: Enable hop detection channel by channel;

COS latch register: stores the instantaneous level of the jump when an interrupt is triggered;

Interrupt status/clear register: Identify interrupt groups and clear interrupt flags.

2. Isolate DO registers (7442/7444)

Batch output register: After writing the level, send synchronous start instructions for unified output;

DO Read Back Register: Read the current hardware output status;

Default configuration register for power on: Write Flash to save the power on level;

WDT safety output register: Configure the protection level in case of watchdog failure.

3. TTL IO register (universal across the entire series)

Direction configuration register: set input/output channel by channel;

TTL read/write register: TTL input read, TTL output write.

4. WDT and system control registers

WDT Count Load Register: Set timeout duration;

Global control registers: WDT switch, safety output enable, hot reset hold switch, interrupt clear bit;

The document fully lists all register offset addresses, bit definitions, read-write properties, reset default values, and supports independent low-level C/C++development.

Software development support

Windows driver library PCIS-DASK: provides standard DLLs, compatible with Windows development languages such as VB/VC/Delphi;

Bottom level C/C++example: The register chapter in the manual is accompanied by read-write logic, which can directly operate hardware registers;

The supporting tools are integrated on the driver CD and the complete development package can be downloaded online.

Product application scenarios

Automated production line: sensor batch signal acquisition, solenoid valve/relay cluster control;

Testing and measuring equipment: tooling IO signal triggering, multi station status monitoring;

Building/computer room monitoring: switch alarm, access control, fan and pump linkage;

Rail transit and onboard industrial control: isolated digital signal interaction in strong electromagnetic environments;

Safety equipment: watchdog fault protection, equipment out of control safety cut-off.