ADLINK PCI-9114 (A) Multi functional PCI Data Acquisition Card

ADLINK PCI-9114 (A) Multi functional PCI Data Acquisition Card

Overall product positioning and core hardware specifications

PCI-9114 (A) is a 32-bit plug and play PCI bus multifunctional hybrid acquisition card that integrates 16 bit analog acquisition, isolated digital IO, 8254 multi-channel timers, hardware triggering, and 1K depth FIFO. It is designed for industrial process monitoring, medical equipment, sensor measurement, thermocouple acquisition, and laboratory automation.

1. Core differences between the two major models

Model: ADC chip, single channel, maximum sampling rate, programmable PGA gain, gear matching function, hardware

PCI-9114 LTC1605 100KHz HG：1/10/100/1000

DG: 1/2/4/8 only triggered by internal clock, without external multifunctional CN4 interface

PCI-9114A LTC1606 250KHz with HG/DG two sets of gain added CN4 external terminal, pre trigger Pre Trigger, programmable counter 0

2. Analog input (A/D) core parameters

Channel configuration: 32 single ended (SE)/16 differential (DI), jumper JP1 switching;

Resolution: 16 bit successive approximation ADC, bipolar input;

Input withstand voltage: Continuous ± 35V overvoltage protection, input impedance 10M Ω;

Isolation cold end temperature measurement CJC: JP2 jumper enabled, can collect thermocouple cold end temperature;

Cache: 1024 word on-chip FIFO, supports batch read with half full interrupt;

Trigger methods: software trigger, internal timer clock trigger, PCI-9114A with additional support for external hardware trigger, pre trigger;

Data transmission: polling, conversion completion EOC interrupt, FIFO half full interrupt.

3. Isolate digital IO (5000VRMS optoelectronic isolation)

16 isolated digital input IDI: 0~24V compatible, non-polar, 4 independent common terminal EICOM;

16 isolated digital output IDO: Darlington emitter output, single channel maximum 500mA, total 8 channels simultaneously 60mA, compatible with relays, indicator lights, solenoid valves;

Output supports inductive load freewheeling circuit, with external power supply of 5-50V.

4. 8254 Programmable Timer Counter (3 independent counters)

Counter 1+2 cascaded to generate A/D sampling clock reference;

PCI-9114A counter 0 can be externally clock/gate controlled for event counting, pulse output, and pre trigger control;

Supports all 6 working modes of 8254, with a reference internal 2MHz clock.

5. Electrical and environmental indicators

Power supply: PCI slot+5V,+12V power supply;

Working temperature: 0-60 ℃, storage: -20~80 ℃, humidity: 5-95%, no condensation;

Board size: PCI-9114 old version is 200mm long, C2/9114A shortened to 175mm, standard PCI full height baffle.

Hardware Installation, Jumper and Interface Definition

1. Packing list

Collecting card body, driver tool CD, paper user manual; The matching terminal board can be equipped with ACLD-9137/9188 and DIN-37D rail terminal block.

2. Electrostatic operation specifications

The card contains CMOS/optocoupler sensitive components, and must be disassembled with anti-static wristbands and pads. It is forbidden to touch PCB components with bare hands.

3. Card jumper function

JP1: Analog input mode switching (Single End/Differential);

JP2: Cold end compensation CJC sensor enabled/disabled, wiring logic is different in SE/DI mode;

JP4 (only 9114A/C2 and later): Counter 0 function switch (pre triggered controller/user universal timer).

4. External connector pins

CN1 (37 pin DB, analog input main interface): 32 single ended/16 differential AI channels, ± 12V auxiliary power supply, analog ground AGND;

CN2 (DB): 16 isolated digital input IDI grouping pins;

CN3 (DB): 16 isolated digital output IDs, external load power Vpower, isolated ground EOGND;

CN4 (only 9114A) 10 pin pin pin: external trigger ExtTrig, pre trigger PreTrig, counter clock/gate/output, onboard 5V, system ground.

5. Installation process

Shutdown and power off → Anti static operation → Set board jumper → Insert any 32-bit PCI slot → Secure baffle → Power on recognition plug and play hardware, install matching driver software.

Bottom Layer Explanation of I/O Register (Reference for Bare Programming)

PCI resource allocation: PnP BIOS automatically assigns base addresses, interrupts IRQ, and prohibits manual modification of conflicting resources; Divided into three groups: PCI configuration registers, local controller registers, and board function registers.

Core register grouping:

A/D channel/gain/trigger control register: set scan endpoint, PGA amplification factor, trigger source;

FIFO status register: empty, half full, full, ADC busy status flag;

Dual interrupt control registers INT1/INT2: INT1 optional EOC conversion completed/FIFO half full; INT12 is a timer interrupt;

8254 Counter Register: Three 16 bit counter read/write and control words;

DI/DO read-write registers: read/output all 16 digital signals at once;

All registers are 16 bit read-write, and 32-bit FIFO data registers simultaneously return ADC values and channel numbers.

Hardware Working Principle

1. Complete process of A/D acquisition

Signal input: JP1 switching single ended (floating ground signal)/differential (suppressing common mode interference, preferred for industrial long lines); Every 8 channels are grouped to share a common VDD;

PGA programmable amplifier HG/DG two sets of ranges, switch input voltage range through register configuration gain;

Channel scanning automatic scanning mode cyclically collects data from channel 0 to the set endpoint;

Trigger system

Software trigger: write register for single conversion;

Timer trigger: 8254 frequency division output with fixed sampling rate, suitable for continuous steady-state acquisition;

External trigger (9114A): External falling edge initiates acquisition;

Pre Trigger (9114A exclusive): Continuously caching data, automatically stopping after collecting N points after external triggering, used for fault transient capture.

Three data transmission mechanisms

Software polling: cyclically read FIFO empty flag, low rate simple scenario;

EOC single conversion interrupt: triggers an interrupt every 1 point collected, suitable for low-speed high-precision single point measurement;

FIFO Half Full Interrupt: Cache 512 points to trigger an interrupt, significantly reducing CPU usage, preferred for high-speed data acquisition.

Numerical conversion formula: Voltage=(AD raw value x 10) ÷ (32768 x gain), 16 bit data range -32768~32767.

2. Design of Dual Interrupt System

The board only occupies one PCI IRQ, but internally distinguishes between INT1 and INT2 interrupt sources. The software reads the interrupt status register to distinguish events. After interrupt processing is completed, the register must be written to clear the interrupt flag, otherwise the interrupt service program will freeze.

3. Isolate DI circuit

PC3H4 optocoupler with non-polar input, 2.4K current limiting resistor, divided into 4 independent isolated common terminals, can be connected to external source/drain sensors.

4. Isolate DO circuit

Darlington driver+freewheeling diode, suitable for inductive loads such as relays and solenoid valves, external independent power supply of 5-50V to prevent board circuit burnout.

5. 8254 Timer Architecture

Counter 1 and 2 are connected in series to generate an ADC sampling clock; Counter 0 (9114A) independently leads out external clock, gate control, and output pins, supporting frequency measurement, pulse generation, and pre trigger counting.

C/C++Advanced Development Library (DOS/Windows Dual Interface)

Library classification

DOS: Pure C function library; Windows: W_ prefix DLL library, supporting all DLL calling languages such as VB, VC, Delphi, C #, etc.

Core API grouping:

Initialization/reset of the board: _9114_initial, _9114_Software-Reset;

Digital IO read and write: _9114-DI, _9114-DO;

ADC basic operations: setting channels, gains, trigger modes, software triggers;

Data reading: single point reading, batch polling, 32-bit reading with channel number;

FIFO and interrupt collection: half full polling, EOC interrupt, FIFO half full interrupt start stop;

8254 Timer: Frequency division configuration, counter 0 start stop and reading;

Interrupt management: interrupt source selection, interrupt clearing, status query.

Function naming convention: Hardware model function name, Windows version adds W prefix; Unified collection of variables for supporting standard data types (U8/I16/I32, etc.).

Calibration and Supporting Tools

1. ADC hardware calibration

Onboard 5 adjustable potentiometers VR1~VR5, respectively used for ADC zero point, full range, PGA pre/post offset, and cold end compensation calibration; Calibration requires a five and a half digit high-precision multimeter, a standard DC voltage regulator, and multiple sets of calibration steps including single end/differential and thermocouple CJC. It is recommended to recalibrate within 3 months for industrial environments and within 6 months to 1 year for laboratories.

2. Supporting tool software

9114fil: compatible with the old version PCI-911 Rev.B2, providing hardware configuration, calibration, IO/ADC function testing menu;

9114AUtl: compatible with PCI-9114A/C2 new version, with the same functionality as above;

I-EEPROM: a low-level tool that enables/disables hardware interrupts on the board.

Appendix Content

Appendix A 8254 Timer Complete Manual: 6 Working Modes, Control Word Format, Read/Write Timing;

Appendix B Wiring Schematic: A complete hardware wiring diagram for simulating single ended/differential, thermocouple CJC, isolation DI, resistive/inductive DO, guiding the wiring of external sensors and relays.

Software ecosystem support

The driver library spans DOS/Windows 95/98/NT/2000; Supporting third-party platform drivers: LabVIEW（PCIS-LVIEW）、HP VEE、DASYLab、InTouch、ISaGRAF、InControl、OPC  Server and DAQBench ActiveX controls, allowing for quick setup of testing interfaces without the need for underlying register development.

Product application scenarios

Industrial process monitoring: temperature, pressure, and flow sensor collection;

Thermocouple/RTD temperature measurement equipment (relying on CJC cold end compensation);

Medical biological signal measurement;

Dynamic acquisition of power supply and motor power;

Laboratory automation testing, capture of transient impact signals (pre trigger function);

Production line IO interlocking and relay switch control.