ADLINK PXI-2020/PXI-2022 Synchronous Sampling Multi functional PXI Data Acquisition Card

ADLINK PXI-2020/PXI-2022 Synchronous Sampling Multi functional PXI Data Acquisition Card

Product Overview and Core Features

PXI-2020: 8-channel differential synchronous AI; PXI-2022: 16 channel differential synchronous AI; each channel has an independent ADC, truly synchronized sampling, non multiplex scanning architecture.

Resolution of 16 bits, with a maximum of 250 kS/s per channel; Onboard 16K sample FIFO buffer.

Programmable gain x 1, x 4; Input range ± 10   V, ± 2.5   V.

Transmission method: Query Polling, Scatter Gather bus main DMA for high-speed continuous acquisition.

IO resources: 4-channel programmable TTL DIO; 8 channels of multifunctional AFI auxiliary function IO; 2 channels of 32-bit general-purpose timer/counter GPTC.

Trigger source: software trigger, external digital trigger (SMB-TRG IO/AFI), PXI star trigger PX_STAR, PXI trigger bus.

Four collection triggering modes: pre trigger, post trigger, middle trigger, delay trigger, and support for re trigger.

Multi card synchronization: Reuse PXI backplane trigger bus to implement SSI system synchronization interface, which can distribute time base TIMEBASE, trigger, and convert signals to achieve multi card synchronization.

Automatic calibration: onboard high-precision 5V low drift reference source, software fully automatic calibration, calibration parameters stored in onboard EEPROM.

Four SMB interfaces on the front panel: bidirectional TRG-IO, CLK IN external clock input, CLK OUT0/CLK OUT1 clock output.

Hardware specifications

1. Simulate input AI

Project PXI-2020 PXI-2022

Number of channels 8 differential 16 differential

ADC AD7685 or equivalent, 16 bit AD7685 or equivalent, 16 bit

Single channel maximum sampling rate 250 kS/s 250 kS/s

Input range ± 10   V, ± 2.5   V ± 10   V, ± 2.5   V

Programmable gain x 1, x 4 x 1, x 4

Input impedance 1   G Ω 1   G Ω

Overvoltage protection, power on/off duration ± 30   V, power on/off duration ± 30   V

Common mode voltage range ± 8V ± 8V

Onboard FIFO 16K samples (8192 × 32-bit) 16K samples (8192 × 32-bit)

Data transmission: Polling, Scatter Gather DMA Polling, Scatter Gather DMA

Key AC/DC performance (25 ℃)

Gain x 1: typical offset of ± 0.6 mV, gain error of ± 0.02%; 3dB bandwidth of 1MHz; CMRR 80 dB; SNR 84 dB; ENOB effective bits 13.3 bits; SFDR 87 dB.

2. Digital IO and AFI

DIO: 4-channel bidirectional TTL; Power on pull-down input; 3.3V output, compatible with 5V input; Each drive is ± 24 mA.

AFI 8-channel multifunctional IO: can be used as trigger input/output, timer clock/gate control, and clock conversion; Power on 10K pull-down input; The minimum pulse width is 12.5 ns.

3. Universal Timer/Counter GPTC

Channel: 2 channels of 32-bit up and down counters;

Reference clock: Internal 20 MHz, also supports external clock;

8 working modes: Gate controlled event counting, single cycle measurement, single pulse width measurement, single pulse, re triggered single pulse, continuous pulse, etc;

Software can read real-time count values without interrupting the counting process.

4. Timebase system

Internal clock: onboard 80 MHz oscillator with typical accuracy<± 25 ppm;

External time base sources: front panel SMB CLK IN, AFI, PXI-10M backplane clock, PX_STAR, PXI trigger bus Line0;

Sampling rate calculation formula: Sampling rate=TIMEBASE/ScanIntrv; ScanIntrv is a 32-bit scan interval counter;

External SMB CLK IN: AC coupling, 50 Ω impedance, input amplitude 1-2 Vpp, frequency 1-20 MHz.

5. Front panel SMB interface

Interface function

TRG-IO bidirectional; External digital trigger input/trigger signal output, 3.3V TTL

CLK IN external time base clock input, AC coupled 50 Ω

CLK OUT0/CLK OUT1 same source clock output, 50 Ω impedance, 3.3V square wave

6. Power supply, environment, and machinery

PXI backplane power consumption:+3.3V 1.5A; +5V 1.3A； +12V 0.35A。

Working temperature 0-55 ℃; Storage -20~80 ℃; Humidity of 10-90% RH without condensation.

Appearance: Standard 3U PXI single slot module; The front panel is equipped with a 68 pin VHDCI connector and 4 SMBs.

Signal connection

68 pin VHDCI connector: leads out all AI differential signals, DIO, AFI/GPTC clock gate outputs; Distinguish between analog ground AGND and digital ground DGND.

PXI-2020: The pins of the 8-channel AI channel are not yet connected to NC.

Key points of differential input wiring

Grounding reference source: directly connected to AIH (+), AIL (-), differential mode suppresses common mode noise.

Floating ground source (thermocouple, isolated output): Differential wiring must add bias resistors to provide a DC return path, otherwise drift and abnormal readings will occur. If the source impedance is less than 100 Ω, the AIL side can be directly connected to AIGND.

All AI hardware is fixed in differential mode and does not support single ended mode.

Functional principle and working mode

4.1 AI simulation input acquisition

Data format: Bipolar direct binary encoding; At ± 10V, 1LSB=305.2 μ V; At ± 2.5V, 1LSB=76.3 μ V.

Core counter:

ScanIntrv: Scan interval, divide by 80MHz time base to obtain actual sampling rate;

DataCnt: The total number of scanning samples that need to be collected;

TrigDelayTicks: Delay trigger counting;

ReTrgCnt: Re trigger count.

Four types of triggering acquisition timing

Post trigger: The specified number of samples will only be collected after the trigger is triggered.

Pre trigger: continuous collection, stopping when triggered, saving N samples before triggering; If the sample is insufficient before the trigger arrives, the current trigger will be ignored.

Middle trigger: Simultaneously save M samples before triggering and N samples after triggering.

Delay trigger: Upon receiving the trigger, wait for the set count delay before starting data collection.

Support Re trigger re triggering, multiple triggers for segmented collection.

4.2 Time base and trigger routing

Time base source: internal 80 MHz; Front panel external clock; PXI backplane PXI-10M, PXI_STAR, PXI trigger bus Line0; The time base can output and export to the PXI backplane trigger bus as a multi card synchronous master clock.

Trigger source multiplexer

Software triggered;

Front panel SMB TRG-IO;

AFI[0‑7]；

PXI star shaped PXI-STAR;

PXI triggers bus Line5 (SSI_AD_TRIG).

The trigger signal can be output to the SMB-TRG IO, AFI0, PXI trigger bus Line5 for synchronizing external devices.

4.3 SSI Multi Card Synchronization (PXI Backplane Implementation, No need for External Cable)

Reuse PXI backplane trigger bus as SSI system synchronization interface:

SSI_TIMEBASE: Synchronized Time Base Clock;

SSI_AD_TRIG: Synchronous trigger signal;

SSIOADCONV: Synchronize ADC conversion pulses.

Architecture: One master, multiple followers; Only one card can be set as the output of the Master host for the same timing signal, and the rest of the Slave slaves can receive it; Support multiple 2020/2022 cards to achieve channel expansion and synchronous acquisition.

4.4 Universal Timer Counter GPTC

Two 32-bit counters, each with CLK clock input, GATE gating, Up/Down direction, and OUT output; Supports 8 modes, including counting, cycle/pulse width measurement, single pulse, trigger pulse, and continuous pulse generation.

Reuse AFI multifunctional interface for counter input and output pins.

Automatic Calibration

EEPROM storage: Factory calibration coefficients, and 3 sets of user storable calibration datasets are reserved to record calibration time and ambient temperature, which can be loaded as needed.

Onboard reference source ADR02, 5.000   V; temperature drift ± 3   ppm/℃, long-term stability 50   ppm per 1000 hours.

Operating Procedure:

It is recommended to preheat the board for 15 minutes before performing self calibration;

Perform Auto calibration for automatic calibration without the need for external instrument wiring;

Save the new calibration constants to the EEPROM user storage area;

Load calibration constants at program startup.

The DAC may change during the calibration process, it is recommended to disconnect the external input cable.

Software support

All drivers are included in ADLINK All in One DVD; Supports Windows 98/NT/2000/XP/Vista/Win7.

D2K-DASK: Windows DLL library, which can be called by VC, VB, Delphi, BCB;

LabVIEW driver VI library;

MATLAB support;

ActiveX component DAQBench (4-hour evaluation version).

PXI plug and play, IRQ、 The base address and DMA resources are automatically allocated by the BIOS system without any hardware jumpers on the board; The configuration tool PCI-SCAN can view the system resources of the board.

Hardware installation precautions

Static sensitive devices, disassemble and wear anti-static wristbands and pads;

The PXI chassis is completely powered off, the module is pushed along the guide rail, the catapult is fastened, and the front panel screws are tightened;

Reverse disassembly operation; Do not plug or unplug modules with power on.

Safety points

Indoor use only; Do not block the ventilation of the chassis;

On board lithium batteries, there is a risk of explosion if the wrong model is replaced; Dispose of waste batteries in accordance with regulations;

Do not open the module casing, internal repairs are only for authorized technicians;

If liquid enters or hardware falls and is damaged, it needs to be handed over to the service provider for inspection.