ADLINK PXIe-9852 2-channel 14 bit, up to 200 MS/s synchronous sampling PXIe high-speed digitizer

ADLINK PXIe-9852 2-channel 14 bit, up to 200 MS/s synchronous sampling PXIe high-speed digitizer

Product Overview and Core Features

Analog acquisition: 2-channel single ended synchronous 14 bit ADC; The maximum sampling rate is 200 MS/s, and the frequency can be divided as low as about 3.05 kS/s; Analog input -3dB bandwidth of 90 MHz.

Simulation front-end: software AC/DC coupling; AC coupling -3dB cut-off frequency of 11 Hz; impedance software switching of 50 Ω/1 M Ω; three range: ± 0.2 V, ± 2 V, ± 10 V.

Important warning: When using ± 10V range under 50 Ω impedance, the effective value of the input sine signal should not exceed 7 Vrms, otherwise the hardware will be damaged; 1   M Ω impedance can withstand ± 10   V overvoltage.

Unique hardware function: Hardware data averaging mode, which performs waveform averaging point by point after multiple data acquisition triggers, can improve equivalent measurement resolution, and supports 16/32-bit output.

Onboard storage and bus: 1 GB onboard memory; PCIe Gen2 x4； Support Scatter Gather DMA; The maximum single transmission capacity in non clustered mode is 8 MB. Enabling clustered mode is not limited by continuous memory and supports ring multi buffering.

Clock system: Internal synthesizer 200 MHz clock; Support external sampling clock on the front panel and external reference of 10 MHz; Supports backplane PXI_CLK10 and PXIe_CLK100 for multi module synchronization.

Trigger interface enhancement: In addition to the external digital trigger input TRG IN, an additional TRG OUT trigger output SMA interface is provided. The output pulse width is software programmable (50 ns~10 μ s) and can drive a 50 Ω load.

Automatic calibration: onboard+2.5   V,+5   V high-precision reference sources, no need for external instrument self calibration; EEPROM stores two sets of calibration coefficients.

List of SMA interfaces on the front panel

CH0, CH1: Two analog inputs; The blue LED indicates the operational status of the corresponding channel collection;

CLK IN: External reference clock/external sampling clock input;

TRG IN: External digital trigger input;

TRG OUT: Digital trigger output.

Key electrical specifications

Analog input

Item Parameter

Channel 2 single ended synchronization, 14 bit ADC

The maximum sampling rate is 200 MS/s, and the minimum is 3.05 kS/s

3dB bandwidth of 90 MHz

Range ± 0.2   V, ± 2   V, ± 10   V

Input impedance software switch 50 Ω/1 M Ω

Coupling AC/DC, AC coupling -3dB=11Hz

Misalignment error ± 1mV

Gain error ± 0.65%

Crosstalk -80 dB (± 0.2V, ± 2V range)

Data format 16 bit 2 complement, valid 14 bits, low 2 bits constant 0, software discard

The dynamic indicators (SNR, THD, SFDR) vary with range and impedance, and the signal-to-noise ratio of some ranges is slightly lower in 50 Ω mode than in high impedance mode.

Time based clock

Internal crystal oscillator accuracy<± 25 ppm;

External reference clock: 10 MHz, input amplitude 500 mVpp~5 Vpp;

External sampling clock: 40 MHz to 200 MHz, input amplitude 1 Vpp to 5 Vpp;

PXI backplane PXI_CLK10 and PXIe_CLK100 can be used as references;

By using a 16 bit ScanIntrv scanning interval counter to divide the 200 MHz main clock, a lower sampling rate can be obtained.

Trigger the system

Trigger source: software trigger, external digital trigger (TRG IN), CHO/CH1 analog trigger, PXI_STAR, PXIe-DSTARB differential star trigger PXI Trigger Bus [0‑7]。

External digital input TRG IN: 3.3V TTL, 5V withstand voltage; VIL=0.8V，VIH=2.0V； The minimum pulse width is 20 ns; the rising/falling edge is optional.

Digital trigger output TRG OUT: 5V TTL level; The pulse width software can be selected from 50 ns, 100 ns, 150 ns, 200 ns, 500 ns, 1 μ s, 2 μ s, 7.5 μ s, and 10 μ s; Can directly drive a 50 Ω load.

Simulated trigger: CHO/CH1 optional, trigger level software setting, supports positive/negative slope.

Trigger export: The module can act as a Master to output triggers to the PXI Trigger Bus and synchronize with other slave cards.

All trigger working mode

Post Trigger: Collect data after triggering;

Pre Trigger: Save the sampling points before triggering;

Middle Trigger: Independently configure the number of sampling points before and after triggering;

Delayed Trigger: After receiving the trigger, wait for a delay before starting the collection;

Re Trigger: Only supports post trigger and delayed trigger; Hardware automatically captures waveforms multiple times; There is a minimum time interval for triggering again;

Data Average Hardware Average Mode: Only post trigger/delayed trigger available; Repeatedly trigger the waveform and calculate the hardware average point by point; Output 16 bit or 32-bit signed integers; Formula: To increase the resolution of n bits, the number of re triggering times is required (R=4 ^ n); Require the tested signal to have stable period and amplitude.

Hardware counter parameters

Counter bit width description

ScanIntrv 16 bit clock division; Sampling rate=200   MS/s ÷ ScanIntrv

DataCnt 28 bit single acquisition, number of samples per channel

TrigDelayTicks 16 bit delay triggered clock beat

ReTrgCnt 31 bit trigger count, limited value in average mode

Mechanical, environmental, and power consumption

Size: 160   mm (W) × 100   mm (H); Standard PXIe module;

Working temperature: 0-55 ℃; Storage -20~80 ℃; Humidity 5-95% without condensation;

Power consumption:+3.3V standby 766mA, full load 782mA;+12V standby 882mA, full load 970mA.

Software Architecture (Old Version WD-DASK, Same Source as PXIe-9848, Non MAPS)

Business drivers require authorization codes; Unauthorized, only 2-hour demo version can be run.

WD-DASK: Bottom layer driver+DLL dynamic library; Supports Windows XP/7/8; Can be called by VC++, VB, Delphi, etc.

DAQPilot SDK high-level suite:

Windows Universal SDK: Supports VB.net, VC.net, BCB, Delphi;

DAQPilot for LabVIEW；

MATLAB Toolbox Adapter.

DMA Transfer Instructions

Full speed 200 MS/s dual channel total throughput 800 MB/s, capable of continuous streaming within PCIe Gen2 x4 bandwidth;

Onboard FIFO for high-speed buffering; Distributed aggregation DMA linked list processing system for fragmented memory, supporting 64 bit addresses (supporting memory larger than 4GB).

Hardware installation

Electrostatic sensitive devices; Prohibit hot plugging and unplugging; Disassembly and assembly must be completely powered off, and anti-static wristbands and pads must be worn.

Turn off the power supply of the PXI chassis and keep the power cord connected for grounding and anti-static purposes;

Align the module with the slot rail of the chassis and push it in. Tighten the pop-up handle and hear a click. Tighten the panel fixing screws;

Power on and install the WD-DASK driver recognition hardware.

Packing list: PXIe-9852 module, All in One CD, Quick Start Guide.

Multi module synchronous SSI mechanism

The dual channel clock within a single module triggers natural synchronization.

Clock synchronization: All modules share the same reference clock source: PXI_CLK10/PXIe_CLK100/external 10 MHz reference.

Trigger synchronization

Single Master Multi Slave Architecture; Master outputs SSI_TRIG1 to a certain PXI Trigger Bus; Slave triggers the source selection corresponding to the bus.

If the Pre Trigger/Middle Trigger mode is used from the module: output the pre_data.rady ready signal from the module to other idle PXI trigger buses; The Master only outputs the trigger after receiving all the ready signals from the slave modules to ensure synchronization.

Appendix A Calibration Mechanism

EEPROM is divided into 2 storage banks

Bank0 (factory area, write protected): Factory calibration parameters will not be overwritten by self calibration; By default, Bank0 is loaded upon startup.

Bank1 (User Area): Save user Auto Calibration automatic calibration results; The software can be set to load Bank1 by default upon startup and permanently write to EEPROM.

Auto Calibration Automatic Calibration

Use onboard+2.5V/+5V internal reference source without the need for external instruments; Compensation gain and offset drift with temperature and time;

Operation suggestion: Preheat for at least 20 minutes when powered on, disconnect the external input cable and perform calibration again;

The driver automatically compensates for calibration delay internally, and the user program does not require additional processing.