ADLINK USB-2405 24 bit dynamic signal acquisition module

ADLINK USB-2405 24 bit dynamic signal acquisition module

Product positioning and core applications

1. Product Definition

USB-2405 is a USB2.0 bus powered 4-channel synchronous 24 bit ∑ - Δ dynamic signal acquisition module, which natively supports IEPE piezoelectric sensor excitation and is designed for high-precision vibration and noise dynamic measurement. It does not require an external power supply and is portable and plug and play.

2. Typical application scenarios

Equipment vibration testing, rotating machinery status monitoring, acoustic noise measurement, environmental noise analysis, and impact vibration collection.

3. Core hardware highlights

4-channel synchronous sampling, with a maximum of 128kS/s for a single channel; 24 bit ultra-high resolution, built-in digital anti aliasing filter;

Software switching AC/DC coupling, with built-in 2mA IEPE constant current excitation for each channel, compatible with acceleration sensors and microphones;

Rich triggering system (software/analog/digital), supporting multiple acquisition modes such as pre triggering, door triggering, and intermediate triggering;

2-channel multifunctional 3.3V TTL digital IO, capable of counter, PWM pulse, synchronous clock, and external triggering;

USB bus power supply, no external power supply; BNC standard analog interface, terminal digital IO;

Multiple installation methods: desktop upright, DIN rail, wall mounted, suitable for laboratory and industrial control cabinets.

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Complete hardware and electrical specifications

3.1 General Physical/Power Parameters

Interface: High speed USB 2.0 Mini-B; The whole machine is only USB compatible 5V@400mA Power supply, no adapter required;

Size: 156.5 × 114 × 41.3mm; Equipped with a multifunctional bracket;

Working temperature range: 0-55 ℃, storage: -20~70 ℃; Humidity range of 10% to 90% without condensation.

Interface panel: 4-channel BNC analog input, 4-pin spring terminal, 2-channel GPIO (GPI00/GPI01+dual DGND).

3.2 Simulated input AI core indicators (4-channel synchronization)

ADC: 24 bit Sigma Delta, built-in multi-stage linear phase anti aliasing FIR filtering;

Sampling gear:

High resolution mode: 1kS/s~52.734kS/s, noise of 50 μ Vrms;

High speed mode: 52.734kS~128kS/s, noise 65 μ Vrms;

The input range is fixed at ± 10V, with LSB only 1.19 μ V; 8k point global FIFO cache;

Input mode software optional: differential (common mode rejection) 60dB@20Hz ~1kHz)/pseudo differential;

Coupling: AC (-3dB cut-off 0.4Hz, isolated DC bias)/DC direct pass; Enable IEPE to automatically switch AC coupling;

IEPE incentive: Each channel can choose 0/2mA constant current, compliant voltage 24V;

Protection: Input ± 60V overvoltage protection; Channel crosstalk as low as -102dB at 1kHz;

Dynamic performance (typical at 25 ℃): Dynamic range of 100dB at 1kHz, SFDR of 104dB, THD as low as -94dB.

3.3 Multi functional digital IO (2-channel 3.3V TTL)

Only one function can be enabled at a time, software switching:

Static DI/DO: default power on input, pull-down; Output maximum 24mA;

Frequency/event counter: up to 4MHz;

PWM pulse output: up to 4MHz, software configuration cycle and duty cycle;

External digital trigger input (edge trigger, minimum pulse 20ns);

Multi card synchronous sampling clock input (1k~128kHz continuous clock).

Whole machine structure and three installation methods

Supporting integrated multifunctional bracket, three fixing schemes, with dimension drawings:

Desktop upright: The module is inserted into the bracket buckle and placed directly on the tabletop;

DIN rail installation: with rail kit, clip fixed to standard industrial DIN rail;

Wall mounted installation: Reserve 4 Φ 3.4 installation holes on the bracket, and fix the wall with flat head screws;

Backboard rotation ID dialing: 8 device numbers from 0 to 7, set different IDs to avoid conflicts when multiple cards are connected simultaneously.

Process of unboxing and power on connection

List of unboxing accessories: USB-2405 host, multifunctional bracket, 2-meter USB cable, DIN rail kit, driver CD, quick guide;

Operation sequence: Turn on the computer → Install the CD driver UD-DASK/DAQPilot first → Connect the USB cable to the module;

Power on recognition: firmware loading takes about 6 seconds, the rear indicator light turns from amber to green, and Windows Device Manager can recognize ADLINK USBDAQ devices;

Troubleshooting: Unable to identify mostly due to insufficient power supply to the USB port (this device requires 400mA current), replace the rear USB 2.0 interface.

Simulate the complete working principle of data acquisition

6.1 Front end signal configuration rules

Recommended input mode for signal source type

Floating sensor (IEPE microphone/accelerometer) pseudo differential

Ground reference voltage source differential

IEPE pathway: A 2mA constant current source is connected in series with a DC blocking capacitor to automatically filter out the DC bias of the sensor, and only output the vibration AC signal to the ADC.

6.2 Sampling and Data Transmission

On chip DDS clock generator, with a sampling resolution of 0.0003Hz and gears distinguished by oversampling multiples of 512/256;

Two transmission modes:

Polling mode: Real time reading of the latest values, no cache, suitable for low-speed monitoring;

Continuous block transfer: FIFO cache batch upload, buffer size needs to be 256 integer multiples, suitable for long-term vibration recording;

Frequency response characteristics: upper bandwidth limit ≈ 0.49 x sampling rate, minimal in band ripple, and out of band suppression of over 100dB to suppress aliasing noise.

Complete triggering system (core collection function)

7.1 Three types of trigger sources

Software trigger: Code call directly initiates data collection without the need for external circuits;

Simulation channel trigger: Choose 4 AI channels as trigger sources, supporting two types of judgments: above threshold/below threshold;

Digital external trigger: GPIO detects rising/falling edges, TTL level compatible.

7.2 All Collection Trigger Mode

Post: After triggering, store the specified number of points; Support multiple triggers;

Pre trigger: store N points before triggering, with a total cache of ≤ 8k points; Discard data before triggering;

Delay triggering: After triggering, the specified sampling point is delayed before recording; Support for re triggering;

Middle trigger: The trigger point is located in the middle of the acquisition segment, and the number of points before and after is independently set;

Gated: Continuous acquisition during high/low level duration, stopping when the level disappears.

Calibration mechanism (ensuring long-term measurement accuracy)

Factory calibration: The calibration parameters are fixed to the original factory partition of the onboard EEPROM and cannot be overwritten;

Auto Cal: No need for external standard sources, relying on onboard precision references; Preheat for 15 minutes before operation;

User storage partition: New correction coefficients generated by self calibration can be stored in the EEPROM user area, allowing for one click restoration of original factory calibration at any time;

Calibration logic: The FPGA has a built-in TrimDAC to correct offset and gain errors, eliminating measurement deviations caused by temperature drift.

Complete software ecosystem (Windows)

9.1 Bottom layer development driver library

UD-DASK kernel driver: 32/64 bit Windows support, providing C/C++underlying APIs; Minimum version 1.2.2.0627;

DAQPilot Development Kit: Provided NET, ActiveX, LabVIEW VI, MATLAB Toolbox, minimum version 2.6.1.0628.

9.2 Programming free testing tool U-Test

Equipped with a free visual upper computer, all functional tests can be completed without code:

Function: Real time display of channel waveform acquisition, FFT spectrum analysis, AI coupling/IEPE switch control, digital IO read-write, PWM/counter debugging, data log saving;

Interface partitioning: device tree, waveform window, FFT window, channel parameter configuration, digital control panel.