ADLINK cPCI-9116 3U CompactPCI 64 channel 16 bit 250KS/s analog acquisition card

ADLINK cPCI-9116 3U CompactPCI 64 channel 16 bit 250KS/s analog acquisition card

Product Core Features

1.1 Simulated Input AI Core Capability

Flexible channel configuration: 64 single ended (SE)/32 differential (DI), supporting mixed single ended and differential acquisition, software switching without jumpers

ADC specification: LT1606 chip, 16 bit resolution, maximum sampling rate of 250KS/s

Onboard cache: 1024 word hardware FIFO; 512 word channel gain queue (customizable acquisition channel order, gain, input mode)

Programmable gain: × 1/× 2/× 4/× 8

Input voltage range

Bipolar: ± 5V, ± 2.5V, ± 1.25V, ± 0.625V

Monopolar: 0~10V, 0~5V, 0~2.5V, 0~1.25V

Hardware specifications

Common mode rejection CMRR: up to 93dB (± 0.625V range)

Accuracy: 0.01%~0.04% of full scale

Input impedance 100M Ω//6pF, supporting ± 35V continuous overvoltage protection

Time base clock: built-in 24MHz; External clock 1MHz~24MHz compatible with TTL

5 hardware triggering modes: software triggering, pre triggering Pre, post triggering Post, intermediate triggering Middle, delayed triggering Delay

Three data transfer methods: software polling, EOC conversion completion interrupt, FIFO half full interrupt, PCI main DMA (high-speed CPU free)

1.2 Digital IO DIO

8-channel TTL digital input+8-channel TTL digital output, standard TTL level specification, batch operation of readable and writable registers.

1.3 Universal Timer GPTC

Single channel 16 bit up/down counter, clock options include built-in 24MHz/external up to 20MHz, supports gate control and up/down counting hardware pins, and provides 2 standard counting modes.

1.4 General Electric and Structural Specifications

Interface: 100 pin SCSI-II J1 connector, integrated AI/DI/DO/timer/external trigger/clock/± 15V/+5V auxiliary power output

Power consumption:+5V 560mA,+3.3V 100mA; ± 15V output maximum 5mA,+5V output maximum 500mA

Temperature range: working from 0~60 ℃, storage from -20~80 ℃, humidity from 5~95%, no condensation

Size: Standard 3U CompactPCI board

1.5 Complete software ecosystem (MAPS platform)

Linghua Unified MAPS Measurement Automation Software Suite, all included with CD, commercial drivers require authorization, no authorization, only 2-hour trial:

MAPS Core (essential underlying layer)

ACE Connection Manager: Device Identification, DMA Cache Configuration, Alias Settings, Soft Front Panel (Visual Waveform Collection)

System tools: Chassis monitoring, device resource management, hardware self-test tools

MAPS/C: C/C++Development SDK, header files API、 Engineering example, supports Windows

MAPS/LV: LabVIEW specific driver VI library, supporting routines

MAPS/C #:. NET C # Development SDK (documentation to be released soon)

Support system: Full Windows series, PCI plug and play automatic allocation of IRQ and IO base addresses, no need for jumper configuration

Hardware installation and anti-static specifications

2.1 Packaging List

CPCI-9116 board, user manual, accompanying All in One software CD, software installation guide; Contact the dealer for missing accessories and keep the original packaging.

2.2 Anti static mandatory operation

The board contains static sensitive chips, and the operation must:

Grounding anti-static pad+anti-static wristband;

Only hold the edge of the board and do not touch the chip or gold fingers;

Open the box and check that the PCB components are not loose, and that the IC socket is pressed firmly;

Hardware damage is strictly prohibited from powering on.

2.3 PCI Plug and Play Mechanism

No IRQ, DMA, or base address jumpers, system BIOS automatically allocates resources when powered on;

Troubleshooting: Startup abnormalities are often caused by interrupt conflicts, adjust BIOS PCI resource allocation parameters.

2.4 PCB Layout

Standard 3U cPCI version, front integrated ADC, FIFO, FPGA, power conversion, 100 pin rear connector.

100 pin J1 connector and signal wiring

3.1 Classification of connector pins

Simulate input AI

Single ended channel: AI0~AI63; Differential channel AIHx (positive)/AILx (negative), a total of 32 differential channels;

U_CMMD user common mode pin: suppresses multi-channel common mode noise;

AGND analog ground, independently isolated digital ground DGND.

Digital IO: DI0~DI7 input, DO0~DO7 output, TTL level.

Timer/trigger dedicated pin

ExtTimeBase: External clock input within 24MHz

ExtTrg: External digital triggered edge input

SSH_OUT: Synchronous sampling and holding output (external S/H chip)

GPTC: Counter CLK, GATE, UPDN direction, OUT output

Auxiliary power supply:+15V, -15V, two-way+5V external power supply.

3.2 Three types of analog input wiring methods

Single ended input SE

Suitable for floating signal sources (isolated sensors, thermocouples), all signals are uniformly referenced to the AGND board, with simple wiring but weak resistance to common mode interference.

Differential input DI

Suitable for grounding reference signals, significantly suppressing power frequency common mode noise; The floating source needs to add a bias resistor at the negative end to provide a return path.

User common mode U_CMMD

Multiple reference signals with the same ground are uniformly connected to the U_CMMD pin to eliminate interference caused by multiple ground potential differences.

3.3 Digital IO wiring

TTL bidirectional buffer circuit, DI reads external levels, DO outputs to drive external devices, and shares DGND digital ground.

Core working principle

4.1 Two collection modes

Mode 1: Software Single Point Polling

Software triggers ADC conversion once, polls FIFO empty flag to read data; Conversion period ≤ 4 μ s, suitable for low-speed, asynchronous single point measurement, timing completely controlled by software.

Mode 2: Programmable scanning acquisition (recommended for high-speed synchronous acquisition)

Accurately control the acquisition timing through 4 sets of hardware counters:

SI2 (16 bit): Single channel sampling interval;

DIV (9 bits): A single scan contains the number of channels (corresponding to gain queue entries);

SI (24 bit): Complete scan repetition cycle;

SC (24 bit): Total number of scans after triggering;

Constraint: SI ≥ SI2 × DIV, with a maximum sampling speed of 250KS/s.

SSH_OUT synchronous output: Each round of scanning outputs pulses to drive the external synchronous sampling and holding circuit, achieving multi-channel synchronous sampling.

Channel gain queue: up to 512, custom collection order, channel, gain, input mode, cyclic collection.

4.2 Five types of triggering complete working logic

Software trigger: Program call starts collection, no external signal, fixed timing scanning.

Pre Trigger: Continuous collection, only retaining M sets of scan data before the external trigger arrives; M-enable can block early triggers and ensure a fixed pre acquisition length.

Middle Trigger in the middle: simultaneously saves the M scans before triggering and N scans after triggering, suitable for capturing the complete waveform before and after the event; Support M-enable filtering for early triggers.

Post Trigger: The collection of N sets of scans only starts after the external trigger is reached, which is suitable for capturing subsequent waveforms of events; Support multiple triggers.

Delay Trigger: After external triggering, wait for programmable delay, and then start the acquisition after the delay is over; The delay clock can be selected as a 24MHz reference or ADC sampling clock.

4.3 Three data transmission mechanisms

EOC Interrupt: Trigger interrupt upon completion of each channel conversion, suitable for low-speed real-time processing; Pre/intermediate triggering is not supported.

FIFO Half Full Interrupt: When the cache reaches 512 points, batch reads are triggered to reduce the number of interrupts; Pre/intermediate triggering is not supported.

PCI Main DMA (Recommended High Speed): Hardware directly transfers data to the host memory, with no involvement from the CPU; The only support is pre trigger and intermediate trigger modes, with a maximum of 32M samples collected at a time. Onboard 1K FIFO cache to prevent data loss.

4.4 Universal Timer GPTC Function

Single channel 16 bit up and down counter, with two working modes:

Mode 0 (Terminal Count Interrupt): Count to 0 and output a high level for event counting;

Mode 1 (Frequency Division Generator): N-division pulse output, timing, pulse generation;

Hardware control: external clock, external gate control start stop, UPDN pin switching addition and subtraction counting, software can read and write the current count value.

Safety requirements for the entire machine

Power off the entire machine before installation and maintenance, and restore the chassis cover before powering it back on;

Stay away from liquids and high temperatures, ensure ventilation, and avoid surface burns caused by high temperatures;

Built in lithium battery, there is a risk of explosion when replacing the wrong model, and the waste battery is recycled in compliance with regulations;

Only authorized engineers are authorized to repair. If there is water ingress, damage from falling, or damage to the power cord, it must be returned to the factory.