ADLINK cPCI/PCI-8554+R multifunctional counting/timing card

ADLINK cPCI/PCI-8554+R multifunctional counting/timing card

Product Overview

1. Core hardware architecture

The board is equipped with four 82C54 programmable timing counter chips, totaling 12 16 bit subtraction counters; Equipped with 8-channel digital input DI, 8-channel digital output DO, anti shake filtering circuit, dual interrupt system, PCI bus ASIC controller (compatible with PCI 2.1 plug and play), external signals are led out through a 100 pin SCSI-II female socket.

2. Key characteristics

Flexible configuration of counters

Counter 1-10: works independently, software can be cascaded; Choose 1 from 4 clock sources (external ECLKn, previous COUPn-1, CK1, COUP10); The door control is set to internal high power and normally on by default, and can be connected to an external door control signal.

11. Counter 12: Factory hardware cascaded to form a 32-bit frequency divider, fixed with an 8MHz internal clock; The cPCI version can be externally gated through JP14/JP15, while the PCI version can permanently raise the gating.

The highest input clock is 8MHz, the lowest output frequency after cascading is 0.00186Hz, and the maximum fixed time interval is 536 seconds.

Anti shake and anti shake circuit

Using MC14490 filtering chip, 11 external clocks/interrupts can enable anti shake through JP1~JP11; Choose one of the two anti shake clock DB_CK (2MHz fixed/COUP11 output), the signal needs to maintain 4 DB_CK cycles to determine effectiveness and filter out glitches.

Dual Interrupt System (Single IRQ Channel)

INT1: Internal source, output from COUP12 counter;

INT2: External source, external interrupt input of E_INT;

The software can distinguish interrupt sources, separate switches, and clear interrupt flags, making it suitable for watchdog and external emergency triggering scenarios.

Digital IO

8DI+8DO, TTL level compatible, shared I/O base address 0x18 register (read DI, write DO).

Electrical and Structural

Power supply: 5V 350mA typical, interface leads+5V,+12V, with thermistor overcurrent protection;

Size: 134mm × 107mm; Operating temperature: 0-60 ℃, Storage: -20~80 ℃;

Interface: 100pin SCSI-II connector, with slight differences in pin definitions between PCI and cPCI versions (7 and 16 pins have different functions).

3. Typical application scenarios

Event counting, frequency generator, frequency synthesis, pulse width measurement, low-frequency pulse output, delay control, industrial automation, watchdog timer.

4. Software support

Linghua provides a full platform development kit, all of which come with a CD:

Bottom level C/C++libraries: DOS library Win95 DLL；

Industrial configuration drivers: PCIS-DASK (Win98/NT/2000), PCIS-DASK/X (Linux shared library);

Third party software drivers: LabVIEW (PCIS-LVIEW), HP VEE (PCIS-VEE);

Visual Control: DAQBench ActiveX Control (VB/VC++Rapid Development);

Commercial drivers default to a 2-hour trial period, and formal authorization requires purchasing from distributors.

Quick Get Started and Hardware Installation

1. Packaging List

Board body, user manual, ADLINK matching CD, software installation guide; Missing/damaged items require contacting the dealer and retaining anti-static packaging.

2. Anti static operation specifications

The board contains static sensitive components, and anti-static wristbands and grounding anti-static pads must be used for disassembly and assembly. Only the edges of the board should be used, and touching the chip pins is prohibited; Damage is prohibited from being powered on.

3. Default configuration of jumper wires

PCI-8554 (13 sets of jumpers)

JP1~JP11：ECLK1~ECLK10、E_INT， Default turn off anti shake function;

JP12: Counter11 clock, default 8MHz internal clock;

JP13: Counter 12 clock, default connected to COUP11 (hardware cascading).

CPCI-8554/R additional 2 sets of jumper wires JP14/JP15: controls the gate control of Counter11/12, defaults to VCC normally open, and can switch external GATE11/GATE12 signals.

4. Hardware installation steps

Turn off the power of the computer and peripherals, and release static electricity from the human body;

Modify the jumper wires of the board according to the requirements;

Insert the 32-bit white PCI slot and secure the baffle with screws;

After booting up, Windows Plug and Play automatically recognizes NuDAQ devices and installs drivers according to the instructions on the CD.

5. Detailed principles of counters, clocks, gates, and interrupts

Independent counters (1-10)

The software can freely switch between four clock sources through _8554_SET_cntCLK and supports software cascading of any front and rear channels; Gate control can be externally connected for pulse width/frequency measurement.

Hardware cascade counter (11, 12)

Default 32-bit frequency division, used for generating extremely low frequencies and watchdog timing; JP12/JP13 can be split into two independent counters, with an external ECLK11/ECLK12 clock.

Clock system CK1

CK1 is the global reference clock, choose one: 8MHz internal reference/COUP11 output, configured by _8554_SET-CK1.

Anti shake clock DB_CLK

Choose one: 2MHz fixed/COUP11 output, _8554_SET-DBCLK switching, only used for external clock/interrupt stabilization.

Dual interrupt hardware pathway

COUP12 triggers INT1, and the external signal of E_INT triggers INT2 after stabilization; Two interrupts share a PCI single IRQ, and the software distinguishes the source and clears the corresponding interrupt flag.

6. Definition of 100 pin connector pins

Distinguish between PCI version and cPCI/R version, including:

ECLK1~ECLK12:1~12 counters external clock;

GATE1~GATE10: External gating (11/12 without external pins);

COUP1~COUP12: Counter output;

DI0~DI7 digital input, DO0~DO7 digital output;

External interrupt of E_INT, GOUT1/GOUT2 (GIN1/GIN2 reverse TTL);

+12V,+5V power supply, a large number of GND grounding pins, and NC empty pins.

Bottom Register Manual

Targeting bottom level developers without drivers, all registers are 8-bit, accessed based on BIOS allocated base address Base offset:

PCI Plug and Play Register

PLX PCI9030/9050 bus controller, PCI configuration registers are automatically assigned base addresses by the system BIOS IRQ， Prohibit manual modifications to avoid resource conflicts.

I/O Address Mapping Table

Explanation of offset address function

Base+0x00~0x0F 4 8254 counter registers (read/write count values, mode control)

Base+0x10~0x12 clock source selection control register (CnN1/CnN2, CK1SEL, DBCSIL)

Base+0x18 digital IO register (read=DI input, write=DO output)

Subdivision Register Description: 8254 Counting Register, Clock Mode Control Register, DI Read Only Register, DO Write Only Register, with each bit corresponding to the channel configuration.

Signal wiring and typical engineering applications

1. Digital IO wiring specifications

TTL level direct connection to external devices, DI receiving external signals, DO output control, matched with common GND.

2. Five standard application cases (including wiring, calculation, and software demo references)

250kHz square wave generator (single counter)

Internal 8MHz clock, counter 1 division value of 32 (8M/32=250K), gate control suspended normally open, COUP1 output waveform.

1-hour 1-pulse ultra-low frequency generator (three-level software cascade)

Counter1=4000、Counter2=2000、Counter3=3600，8M/4000/2000/3600=1/3600Hz，COUT3  Output 1 pulse per hour.

Pulse width measurement

The measured signal is connected to GATE1, with an internal 2MHz time base. The maximum measurement of a single counter is 32.768ms. The wide pulse can be cascaded in multiple stages to expand the range.

External frequency measurement (1-100kHz)

One counter generates precise gate time, while the other counts external ECLK1 pulses, with frequency=count value/gate duration; External clock enables anti shake filtering to eliminate interference.

Event counter (counting external pulses in 1 second)

11/12 Hardware cascading generates a 1-second timed gate, Counter1 counts ECLK1 external event pulses, and anti shake opens to adapt to mechanical switch inputs.

Dual Interrupt Integrated Application

INT1 sets a timer alarm for the system watchdog, INT2 is triggered by an external emergency stop, and the software distinguishes between two interrupts to handle them separately.

C/C++software function library

Distinguish between DOS library (function prefix _) and Win95 DLL (prefix W_), provide a complete set of operation interfaces, and unify data types (U8/U16/I16/U32, etc.):

Classification of core functional functions

Board initialization

_8554Initialize: Scan multiple 8554 cards in the system, read the base address allocated by BIOS IRQ。

Counter read-write control

_8554Write_Cunter: Write counter number, working mode, initial value;

_8554_ Read_Sunter: Read the current count value and working mode;

_8554_Stop_Sunter: Stop specifying the counter;

_8554_Sead_Status: Read the running status of the counter.

Clock source configuration

_8554_SET_cntCLK: Set the clock source for counters 1-10;

_8554_SET-CK1: Global reference clock CK1 switching;

_8554_SET-DBCLK: Anti shake clock DB_CK switching.

Digital IO read and write

_8554-DO: Output 8-bit data to the DO port;

_8554-DI: Read the status of 8 DI inputs.

Interrupt the entire set of operations

_8554_Set-INT_Control: Interrupt enable switch INT1/INT2;

_8554_Get_iRQ_Status: Query the current triggered interrupt source;

Windows exclusive: W_8554-INT_Enable/W_8554-INT_Disable binds system events;

DOS exclusive: Clear interrupt flag for _8554_LR_IRQ1/_8554_LR_IRQ2.

Return value specification

Unified error code: No error, no PCI BIOS, board not initialized, illegal counter number, illegal mode parameter.