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GE IC697MDL740 24/48 VDC Output, 2 Amp, Positive Logic

two micro DB-9 connectors located on the front panel. The

micro DB-9 connectors require two micro DB-9 to standard

DB-9 adapters, VMIC P/N 360-010050-001.

PMC EXPANSION SITE — The VMIVME-7700

provides one IEEE 1386.1, 5 V PCI mezzanine card (PMC)

expansion site. This expansion capability allows the

addition of peripherals offered for PMC applications. The

PMC site provides for standard I/O out the VMEbus front

panel. An optional I/O connection to the VMEbus P2

connection can be provided.

KEYBOARD and MOUSE PORTS — The

VMIVME-7700 supports a PS/2 keyboard and mouse

through the front panel.

HARDWARE RESET — A hardware reset switch is

accessible from the front panel.

PROGRAMMABLE TIMER — The VMIVME-7700

provides the user with two 16-bit timers and two 32-bit

timers. These timers are mapped in PCI memory space, are

completely software programmable and can generate PCI

bus interrupts.

WATCHDOG TIMER — The VMIVME-7700

provides a software-programmable Watchdog timer. The

Watchdog timer is enabled under software control. Once the

timer is enabled, software must access the timer within the

specified time period, or the output of the Watchdog timer

will reset the unit.

NONVOLATILE SRAM — The VMIVME-7700

provides 32 KB of nonvolatile SRAM. The contents of the

SRAM are preserved when +5 V power is interrupted or

removed from the unit.

CMOS BATTERY — The VMIVME-7700 uses a

holder that permits field replacement of the CMOS battery.

A header and jumper allows the battery to be disconnected

from the circuitry for long-term storage.

ANNUNCIATORS — Indicators for the board status,

+5 V power good, are provided on the front panel. In

addition, two indicators for the Ethernet adapter activity are

located on each RJ45 network connector.

THERMAL MANAGEMENT — The VMIVME-7700

utilizes a passive heat sink that relies on forced air cooling

within the equipment rack at the specified flow rate. Please

refer to the environmental specifications for more

information.

VMEbus INTERFACE — The VMIVME-7700

VMEbus interface is based on the Universe IID high

performance PCI-to-VMEbus interface from

Newbridge/Tundra.

SYSTEM CONTROLLER — The VMEbus system

controller capabilities allow the board to operate as a slot 1

controller, or it can be disabled when another board is acting

as the system controller. The system controller may be

programmed to provide the following modes of arbitration

Round Robin (RRS)

Single Level (SGL)

Priority (PRI)

The system controller provides a SYSCLK driver,

IACK* daisy-chain driver, and a VMEbus access timeout

timer. The system controller also provides an arbitration

timeout if BBSY* is not seen within a specified period after

a BGOUT* signal is issued. This period is programmable

for 16 or 256 µs.

VMEbus REQUESTER — The microprocessor can

request and gain control of the bus using any of the VMEbus

request lines (BR3* to BR0*) under software control. The

requester can be programmed to operate in any of the

following modes:

Release-On-Request (ROR)

Release-When-Done (RWD)

VMEbus Capture and Hold (VCAP)

MAILBOXES — The VMEbus interface provides four

32-bit mailboxes, which are accessible from both the

microprocessor and the VMEbus providing interprocessor

communication. The mailboxes have the ability to interrupt

the microprocessor when accessed by theVMEbus.

INTERRUPT HANDLER — The interrupt handler

monitors, and can be programmed to respond to any or all

VMEbus IRQ* lines. All normal-process VMEbus-related

interrupts can be mapped to PCI INTA# or SERR#

interrupts. These include:

Mailbox interrupts

VMEbus interrupts

VMEbus interrupter IACK cycle (acknowledgment

of VMIVME-7700 VMEbus-issued interrupts)

All error processing VMEbus-related interrupts can be

mapped to PCI INTA# or SERR#. Note: PCI SERR#

initiates an SBC NMI. These include:

ACFAIL* interrupt

BERR* interrupt

SYSFAIL* interrupt

The interrupt handler has a corresponding STATUS/ID

register for each IRQ* interrupt. Once the handler receives

an IRQ*, it requests the VMEbus and, once granted, it

performs an IACK cycle for that level. Once the IACK cycle

is complete and the STATUS/ID is stored in the

corresponding ID register, an appropriate interrupt status bit

is set in an internal status register, and a PCI interrupt is

generated. The PCI interrupt can be mapped to PCI INTA#

or SERR#.

INTERRUPTER — Interrupts can be issued under

software control on any or all of the seven VMEbus interrupt

lines (IRQ7* to IRQ1*). A common ID register is associated

with all interrupt lines. During the interrupt acknowledge

cycle, the interrupter issues the ID to the interrupt handler.

The interrupter can be programmed to generate a PCI INTA#

or SERR# interrupt when a VMEbus interrupt handler

acknowledges a software-generated VMEbus interrupt.

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