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GE IS220PAOCH1A Analog output: 8, 0-20 mA output

From: | Author:Wang | Time :2024-12-18 | 252 visit: | 🔊 Click to read aloud ❚❚ ▶ | Share:

GE IS220PAOCH1A Analog output: 8, 0-20 mA output

The MAX6659MEE can be monitored and controlled on the SMBus at address
0x98 for the V7768/V7769. This will allow the user to monitor and set up the
alarm (OVERT2).
For more information on the Maxim MAX6659MEE contact them directly at:
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3.2 Embedded PCI Functions
The V7768/V7769 provide non-volatile RAM (NVRAM), timers and a Watchdog
Timer via the PCI bus FPGA. These functions are required for embedded and real
time applications. The PCI configuration space of these embedded functions is
shown in Table 3-1.
Table 3-1 PCI Configuration Space Registers
31 16 15 0 Register Address
Device ID 0004 Vendor ID 114A 00h
Status Command 04h
Class Code Revision ID 08h
BIST Header Type Latency Timer Cache Line Size 0Ch
PCI Base Address 0 for Memory-Mapped VME Control registers (BAR0) 10h
PCI Base Address 1 for Memory-Mapped 32 KByte NVRAM (BAR1) 14h
PCI Base Address 2 for Memory Mapped Watchdog and other timers (BAR2) 18h
Reserved 1Ch
Reserved 20h
Reserved 24h
Reserved 28h
Subsystem ID 7768 Subsystem Vendor ID 114A 2Ch
Reserved 30h
Reserved 34h
Reserved 38h
Max_Lat Min_gnt Interrupt Pin Interrupt Line 3Ch
The “Device ID” field indicates that the device is for VME products (00) and
indicates the supported embedded feature set.
The “Vendor ID” and “Subsystem Vendor ID” fields indicate GE’s PICMG®
assigned Vendor ID (114A).
The “Subsystem ID” field indicates the model number of the product (7768).


The V7768/V7769 provide four user-programmable timers (two 16-bit and two
32-bit) which are completely dedicated to user applications and are not required
for any standard system function. Each timer is clocked by independent
generators with selectable rates of 2 MHz, 1 MHz, 500 kHz and 250 kHz. Each
timer may be independently enabled and each is capable of generating a system
interrupt on timeout.
Events can be timed by either polling the timers or enabling the interrupt
capability of the timer. A status register allows for application software to
determine which timer is the cause of any interrupt.
3.3.1 Timer Control Status Register 1 (TCSR1)
The timers are controlled and monitored via the Timer Control Status Register 1
(TCSR1) located at offset 0x00 from the address in BAR2. The mapping of the bits
in this register are shown in Table 3-2.
Table 3-2 TCSR1 Bit Mapping
Field Bits Read or Write
Timer 1 Caused IRQ TCSR1[0] R/W
Timer 1 Enable TCSR1[1] R/W
Timer 1 IRQ Enable TCSR1[2] R/W
Timer 1 Clock Select TCSR1[4..3] R/W
Timer 2 Caused IRQ TCSR1[8] R/W
Timer 2 Enable TCSR1[9] R/W
Timer 2 IRQ Enable TCSR1[10] R/W
Timer 2 Clock Select TCSR1[12..11] R/W
Timer 3 Caused IRQ TCSR1[16] R/W
Timer 3 Enable TCSR1[17] R/W
Timer 3 IRQ Enable TCSR1[18] R/W
Timer 3 Clock Select TCSR1[20..19] R/W
Timer 4 Caused IRQ TCSR1[24] R/W
Timer 4 Enable TCSR1[25] R/W
Timer 4 IRQ Enable TCSR1[26] R/W
Timer 4 Clock Select TCSR1[28..27] R/W
Reserved All Other Bits R/W
All of these bits default to “0” after system reset.
Each timer has an independently selectable clock source which is selected by the
bit pattern in the “Timer x Clock Select” field as shown in Table 3-3.
Table 3-3 Selectable Clock Source for Timers
Clock Ratio MSb LSb
2 MHz 0 0
1 MHz 0 1
500 kHz 1 0
250 kHz 1 1
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