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GE IS220PPDAH1A IS220PPDAH1B Power Distribution System Feedback

From: | Author:Wang | Time :2024-12-18 | 152 visit: | Share:

Each timer can be independently enabled by writing a “1” to the appropriate

“Timer x Enable” field. Similarly, the generation of interrupts by each timer can be

independently enabled by writing a “1” to the appropriate “Timer x IRQ Enable”

field.

If an interrupt is generated by a timer, the source of the interrupt may be

determined by reading the “Timer x Caused IRQ” fields. If the field is set to “1”,

then the respective timer caused the interrupt. Note that multiple timers can

cause a single interrupt. Therefore, the status of all timers must be read to ensure

that all interrupt sources are recognized.

A particular timer interrupt can be cleared by writing a “0” to the appropriate

“Timer x Caused IRQ” field. Alternately, a write to the appropriate Timer x IRQ

Clear (TxIC) register will also clear the interrupt. When clearing the interrupt

using the “Timer x Caused IRQ” fields, note that it is very important to ensure

that a proper bit mask is used so that other register settings are not affected. The

preferred method for clearing interrupts is to use the “Timer x IRQ Clear”

registers described on page 50.

3.3.2 Timer Control Status Register 2 (TCSR2)

The timers are also controlled by bits in the Timer Control Status Register 2

(TCSR2) located at offset 0x04 from the address in BAR2. The mapping of the bits

in this register is shown in Table 3-4.

Table 3-4 TCSR2 Bit Mapping

Field Bits Read or Write

Read Latch Select TCSR2[0] R/W

Reserved All Other Bits R/W

All of these bits default to “0” after system reset.

The “Read Latch Select” bit is used to select the latching mode of the

programmable timers. If this bit is set to “0”, then each timer output is latched

upon a read of any one of its address. For example, a read to the TMRCCR12

register latches the count of timers 1 and 2. A read to the TMRCCR3 register

latches the count of timer 3. This continues for every read to any one of these

registers. As a result, it is not possible to capture the values of all four timers at a

given instance in time. However, by setting this bit to “1”, all four timer outputs

will be latched only on reads to the Timer 1 & 2 Current Count Register

(TMRCCR12). Therefore, to capture the current count of all four timers at the

same time, perform a read to the TMRCCR12 first (with a 32-bit read), followed

by a read to TMRCCR3 and TMRCCR4. The first read (to the TMRCCR12 register)

causes all four timer values to be latched at the same time. The subsequent reads

to the TMRCCR3 and TMRCCR4 registers do not latch new count values,

allowing the count of all timers at the same instance in time to be obtained.

3.3.3 Timer 1 & 2 Load Count Register (TMRLCR12)

Timers 1 & 2 are 16-bits wide and obtain their load count from the Timer 1 & 2

Load Count Register (TMRLCR12), located at offset 0x10 from the address in

BAR2. The mapping of bits in this register is shown in Table 3-5.

Table 3-5 TMRLCR12 Bit Mapping

Field Bits Read or Write

Timer 2 Load Count TMRLCR12[31..16] R/W

Timer 1 Load Count TMRLCR12[15..0] R/W

When either of these fields are written (either by a single 32-bit write or separate

16-bit writes), the respective timer is loaded with the written value on the next

rising edge of the timer clock, regardless of whether the timer is enabled or

disabled. The value stored in this register is also automatically reloaded on

terminal count (or timeout) of the timer.

3.3.4 Timer 3 Load Count Register (TMRLCR3)

Timer 3 is 32-bits wide and obtains its load count from the Timer 3 Load Count

Register (TMRLCR3), located at offset 0x14 from the address in BAR2. The

mapping of bits in this register is shown in Table 3-6.

Table 3-6 TMRLCR3 Bit Mapping

Field Bits Read or Write

Timer 3 Load Count TMRLCR3[31..0] R/W

When this field is written, Timer 3 is loaded with the written value on the next

rising edge of the timer clock, regardless of whether the timer is enabled or

disabled. The value stored in this register is also automatically reloaded on

terminal count (or timeout) of the timer.

3.3.5 Timer 4 Load Count Register (TMRLCR4)

Timer 4 is 32-bits wide and obtains its load count from the Timer 4 Load Count

Register (TMRLCR4), located at offset 0x18 from the address in BAR2. The

mapping of bits in this register is shown in Table 3-7.

Table 3-7 TMRLCR4 Bit Mapping

Field Bits Read or Write

Timer 4 Load Count TMRLCR4[31..0] R/W

When this field is written, Timer 4 is loaded with the written value on the next

rising edge of the timer clock, regardless of whether the timer is enabled or

disabled. The value stored in this register is also automatically reloaded on

terminal count (or timeout) of the timer.

3.3.6 Timer 1 & 2 Current Count Register (TMRCCR12)

The current count of timers 1 & 2 may be read via the Timer 1 & 2 Current Count

Register (TMRCCR12), located at offset 0x20 from the address in BAR2. The

mapping of bits in this register is shown in Table 3-8.

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