MOTOROLA CPCI-6020 CompactPCI Single Board Computer

MOTOROLA CPCI-6020 CompactPCI Single Board Computer

Core hardware specifications

CPCI-6020 is a 6U Eurocard specification single board computer, divided into four models (CPCI-60206E-500/505, CPCI-6020-500/505), with the core difference being whether it comes with USB and Super I/O. The core hardware specifications are shown in the table below:

table

Hardware Category Core Configuration Key Parameters/Remarks

Processor MPC7410 500MHz, PowerPC architecture, with Alti Vec technology, 32-bit data/address bus, supports parity check

L2 cache backend cache 2MB, pipeline burst mode SRAM, supports data bus parity check

Flash dual bank design Bank A: 32MB onboard (1 256Mbit device); Bank B: 1MB slot type (2 512Kbit devices)

Memory (SDRAM) ECC SDRAM requires RAM500 expansion module, single module supports 128MB/256MB/512MB, dual site maximum 2GB; supports single bit error correction/dual bit error correction

Non volatile storage NVRAM/RTC/WDT M48T37V provides 32KB NVRAM, RTC clock, and watchdog; RTC supports seconds/minutes/hours/days/months/years, BCD format

Timing/Watchdog Multi Module Collaborative Dual Harrier ASIC: Each includes 2 32-bit programmable timers and 2 independent watchdogs; M48T37V: 1 programmable timer

Power requirements: multi voltage supply+3.3V: 2.6A typical/3.5A maximum; +5V: 2.8A typical/3.75A maximum; ± 12V: 100mA maximum for each; Voltage tolerance ± 5%

The physical size of the 6U Eurocard complies with the CompactPCI specification and is compatible with standard CPCI chassis rails

Working environment temperature/humidity/airflow Working temperature: 0-55 ℃ (forced air cooling); Storage temperature: -40-70 ℃; Relative humidity: 5% -90% (non condensing); Minimum airflow: 250 LFM (55 ℃ environment)

Hardware configuration and installation

This chapter provides a detailed explanation of the unpacking, jumper configuration, and module installation steps for CPCI-6020. The core operations must be carried out in a power-off state to avoid static electricity damage to the circuit. The core content includes:

Unpacking requirements: If the packaging box is damaged, the carrier's agent must be present to unpack and inspect it, and the packaging materials must be retained for storage/transportation. Before operation, it is necessary to ensure that the working environment meets ESD protection requirements;

Jumper configuration: The board contains multiple configurable jumper caps, which are factory default configurations and can be modified according to needs. The core jumper functions are shown in the following table:

|Jumper number | Function | Factory configuration | Optional configuration|

|J24 | Flash Bank Selection | 2-3 Short Circuit (Bank B enabled, including PPCbug) | 1-2 Short Circuit (Bank A enabled, 32MB)|

|J22 | Harrier Power On Configuration | Fully Disconnected (PUST0-3=1) | 1-2 Short Circuit (PUST0=0), 3-4 Short Circuit (PUST1=0), etc|

|J21 | PMC 66MHz disabled | Disconnected (supports 66MHz) | 1-2 short circuited (enforces 33MHz to avoid disabling secondary Ethernet)|

|J18 | ± 12V enable/disable | Disconnect (enable ± 12V) | 1-2 short circuit (disable ± 12V, affecting some peripherals)|

|J17 | Bank A Flash block locked | Disconnected (unlocked) | 1-2 short circuited (locked more than 1 Flash block, unable to unlock)|

|J20 | Bank A Flash Write Protection | Disconnectable (writable) | 1-2 Short Circuit (Full Flash Write Protection)|

|J19 | Remote switch interface | No jumper | Connect remote Reset/Abort switch, with the same function as the front panel|

Module installation

RAM500 memory module: Each site can install up to 2 modules (bottom+top stacked), which need to be connected to the motherboard through a 140 pin connector. During installation, align the positioning holes and tighten the screws;

PMC module: installed on the top of the motherboard, connected through J11-J14 connectors, supports 32/64 bit PCI interfaces, needs to remove the front panel cover and fix 4 screws;

CompactFlash card: Insert the J15 connector and ensure that Pin 1 is aligned. Before installation, turn off the system power;

Transition module (CPCI-6020-MCPTM-01): installed at the rear of the chassis, communicates with the motherboard through J3/J5 interfaces, and supports PIM/SIM module expansion;

System supporting requirements: To complete the CPCI-6020 system setup, it is necessary to provide a CompactPCI compliant chassis, system console terminal, operating system, CPCI-6020-MCPTM-01 transition module, and connecting cables;

Hot plugging precautions: Supports hot plugging of peripheral boards, and hot plugging of system slots requires HA architecture support; Non hot swappable chassis must be powered off before installing/removing modules to avoid data loss or hardware damage.

Operation instructions

This chapter introduces the front-end panel operations, memory mapping rules, software initialization, and reset operations of CPCI-6020, which are the core basis for device use and program development

Front panel controls

Buttons: ABORT # (repeated design, to avoid accidental touch and trigger MPIC internal interrupt), RESET # (repeated design, to trigger board level reset and signal debounce through Harrier ASIC);

2 LED indicator lights: CPU (green, lit when processor bus is active), BDFL (yellow, lit when BDFL bus is active, software controllable);

Memory mapping: divided into two types: local PCI bus mapping and CompactPCI bus mapping. The local PCI bus includes A/B dual buses, and Bus A supports a fixed rate of 33MHz and interfaces with Ethernet, USB, EIDE and other peripherals; Bus B supports 33/66MHz switching and is compatible with PMC slots and secondary Ethernet; The CompactPCI bus supports A16/A24/A32 addresses, D8/D16/D32 data, and communicates with the backplane through J1/J2 connectors;

Register Mapping: The core register area includes Harrier ASIC's XCSR (Configuration Status Register), MPIC (Multiprocessor Interrupt Controller), EIDE controller, USB controller, etc. The manual provides detailed definitions of the addresses, bit widths, functions, and default values of each register;

Software initialization: The PPCBug firmware completes the initialization of the processor, memory, and PCI devices during power on/reset, and the default configuration can start the operating system without modification; Support modifying board information (such as serial number and bus clock) through CNFG commands, and adjusting firmware parameters (such as automatic startup delay and memory size limit) through ENV commands;

Reset operation

Reset source: power on reset, front panel RESET # button, watchdog timeout, software hard reset (Harrier RSTOUT bit/PBC Port 92), CompactPCI PRST # signal, etc;

Scope of Impact: Different reset sources affect devices differently. Software hard reset affects processors, Harrier ASICs, PCI devices, etc. CompactPCI reset only affects the local CompactPCI bus.

Function module analysis

This chapter analyzes the working principles, interface specifications, and timing performance of each core module of CPCI-6020 from the perspective of hardware architecture. The core content includes:

Core bus architecture: Based on the PowerPlus III architecture, dual Harrier ASICs are used as the system memory controller/PCI host bridge to bridge the processor bus and PCI bus; The Intel 21154 PCI to PCI bridge chip provides local CompactPCI bus expansion and supports 7 peripheral slots; Bus arbitration priority: Processor>Harrier ASIC>External PCI master device;

Core storage module

Flash: Bank A (32MB) is an onboard 16 bit Flash, Bank B (1MB) is a slot type 16 bit Flash, and the reset vector source is selected through J24 jumper; Bank B contains PPC bug debugging firmware, reprogramming may result in firmware loss;

SDRAM: Provided by RAM500 expansion module, supporting ECC checksum (72 bits wide, including 8-bit checksum), each RAM500 module contains 9 SDRAM chips (x8 configuration) and 1 SPD Serial EEPROM, reporting memory configuration through I2C bus;

NVRAM/RTC: The M48T37V device provides 32KB non-volatile storage and RTC function, and battery backup ensures that data is not lost after power failure;

Communication and Expansion Interface

Ethernet: Dual 10BaseT/100BaseTx interface (Intel 82551IT), Primary port default front (RJ-45), Secondary port rear (via transition module); Supports Auto MDI/MDI-X, compliant with IEEE 802.3 standard;

Serial ports: 2 16550 compatible asynchronous serial ports (Harrier UART0/UART1), 1 front-end (RJ-45, DCE configuration), and 1 back-end (via transition module); Two synchronous/asynchronous serial ports (Z85230 ESCC), which need to be extended to EIA-232-D standard through SIM module;

USB: 2 USB 2.0 ports (front, Series A interface), supporting high-speed/full speed/low-speed devices, driven by NEC uPD720101 controller, supporting control/interrupt/batch/isochronous transfer;

PMC slot: 1 32/64 bit PMC slot (J11-J14), supports 33/66MHz rate, supports PIM module expansion I/O function, PMC user I/O signals are routed to the transition module through J3/J5 connectors;

EIDE interface: Supports primary (for connecting to CompactFlash) and secondary (for connecting to external devices) channels, supports PIO accelerated transfer and DMA mode, and complies with ATAPI standards;

Local resources

Timer/Watchdog: Each dual Harrier ASIC contains 2 32-bit programmable timers (1 μ s resolution) and 2 independent watchdogs (timeout can trigger reset or interrupt); M48T37V includes one programmable timer that triggers a hard reset upon timeout;

I2C bus: supports 2 I2C main interfaces, interfaces with Serial EEPROM (VPD storage), SPD memory configuration chips, etc., with programmable communication speed;

Interrupt Controller: MPIC (Multi Processor Interrupt Controller) supports 8 programmable hardware interrupts, supports level/edge triggering, and has configurable interrupt priority;

High availability (HA) feature: supports system slot hot plugging (requires HA chassis), and achieves hot plugging detection through BD_SEL # and HEALTHY # signals; Support bus redundancy arbitration and dual Harrier collaboration to ensure stable system operation.

Safety and Compliance

Safety operation regulations: The equipment has lethal high voltage, and grounding is required during operation. ESD protective equipment must be used, explosive environments are prohibited, unauthorized disassembly of the cover plate is prohibited (only authorized personnel can disassemble the machine), single person maintenance is prohibited, and software must be closed before hot plugging;

EMI compliance: As an A-class digital device, it needs to be used in a compliant chassis. The core requirements include shielding wires for external I/O ports, grounding of cable shielding layers, grounding of chassis rails, and tightening of panel screws. Otherwise, it may result in excessive RF emissions;

Cooling requirement: 250 LFM forced air cooling is required at 55 ℃ environment, with CPU as the main heat source, ensuring smooth heat dissipation channels; Avoid adjacent installation of high-power modules and increase airflow in high-temperature environments;

Data security: Before reprogramming Flash, it is necessary to back up the firmware to avoid overwriting PPC bugs; Before hot plugging modules, it is necessary to shut down the operating system and applications to prevent data corruption or file system crashes;

Environmental compliance: Complies with RoHS 6/6 standards, prohibits harmful substances such as lead and mercury; Abandoned modules must be disposed of in accordance with local regulations.

Supporting resources

Firmware: PPCBug debugging firmware (including debugging and diagnostic functions), supporting memory read and write, breakpoint debugging, assembly/disassembly, self-test, etc; Provide a rich command set (such as MD memory display, GO executable program, HE help), support CNFG/ENV command configuration of system parameters;

Software: Supports VMEexec driver package, USB 2.0 driver, EIDE driver, Floppy controller driver, etc; Compatible with third-party PowerPC architecture applications, available through Motorola sales offices;

Related documents: MPC7410 user manual, Harrier ASIC programming guide, PPCBug firmware user manual, RAM500 module manual, CPCI-6020 programming reference guide, as well as industry standard documents such as CompactPCI, PCI, ISA, etc;

Technical support: The connector signal definition, parts list, and schematic diagram of CPCI-6020 can be obtained through Motorola sales office, and are provided free of charge; Support RISCWatch debugging interface and Mictor debugging connector for easy hardware debugging.