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GE VMIVME-2232 32-Channel Relay Output Board with Built-in-Test

From: | Author:Wang | Time :2024-12-18 | 198 visit: | 🔊 Click to read aloud ❚❚ ▶ | Share:

GE VMIVME-2232 32-Channel Relay Output Board with Built-in-Test

The VMIVME-7807/VME-7807RC provide non-volatile RAM (NVRAM), timers and a
Watchdog Timer via the PCI bus. These functions are required for embedded and real
time applications. The PCI configuration space of these embedded functions are
shown below.
The “Device ID” field indicates that the device is for VME products (00) and indicates
the supported embedded feature set.
The “Vender ID” and “Subsystem Vendor ID” fields indicate GE Fanuc Embedded
Systems’ PICMG assigned Vender ID (114A).
The “Subsystem ID” field indicates the model number of the product (7807).
Table 3-1 PCI Configuration Space Registers
31 16 15 00 Register
Address
Device ID 0004 Vendor ID 114A 00h
Status Command 04h
Class Code Revision ID 08h
BIST Header Type Latency Timer Cache Line Size 0Ch
PCI Base Address 0 for Memory-Mapped VME Control registers (BAR0) 10h
PCI Base Address 1 for Memory-Mapped 32kB NVRAM (BAR1) 14h
PCI Base Address 2 for memory-mapped Watchdog and other timers (BAR2) 18h
Reserved 1Ch
Reserved 20h
Reserved 24h
Reserved 28h
Subsystem ID 7807 Subsystem Vendor ID 114A 2Ch
Reserved 30h
Reserved 34h
Reserved 38h
Max_Lat Min_gnt Interrupt Pin Interrupt Line


The VMIVME-7807/VME-7807RC provide four user-programmable timers (two
16-bit and two 32-bit) which are completely dedicated to user applications and are not
required for any standard system function. Each timer is clocked by independent
generators with selectable rates of 2MHz, 1MHz, 500kHz and 250kHz. Each timer
may be independently enabled and each is capable of generating a system interrupt
on timeout.
Events can be timed by either polling the timers or enabling the interrupt capability of
the timer. A status register allows for application software to determine which timer is
the cause of any interrupt.
Timer Control Status Register 1 (TCSR1)
The timers are controlled and monitored via the Timer Control Status Register 1
(TCSR1) located at offset 0x00 from the address in BAR2. The mapping of the bits in
this register are as follows:
Field Bits Read or Write
Timer 1 Caused IRQ TCSR1[0] R/W
Timer 1 Enable TCSR1[1] R/W
Timer 1 IRQ Enable TCSR1[2] R/W
Timer 1 Clock Select TCSR1[4..3] R/W
Timer 2 Caused IRQ TCSR1[8] R/W
Timer 2 Enable TCSR1[9] R/W
Timer 2 IRQ Enable TCSR1[10] R/W
Timer 2 Clock Select TCSR1[12..11] R/W
Timer 3 Caused IRQ TCSR1[16] R/W
Timer 3 Enable TCSR1[17] R/W
Timer 3 IRQ Enable TCSR1[18] R/W
Timer 3 Clock Select TCSR1[20..19] R/W
Timer 4 Caused IRQ TCSR1[24] R/W
Timer 4 Enable TCSR1[25] R/W
Timer 4 IRQ Enable TCSR1[26] R/W
Timer 4 Clock Select TCSR1[28..27] R/W
Reserved All Other Bits R/W
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