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Home >> GE >> GE VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts
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GE VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts

From: | Author:Wang | Time :2024-12-18 | 80 visit: | Share:

GE VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts

The VMIVME-7807/VME-7807RC provide a programmable Watchdog Timer (WDT)
which can be used to reset the system if software integrity fails.
WDT Control Status Register (WCSR)
The WDT is controlled and monitored by the WDT Control Status Register (WCSR)
which is located at offset 0x08 from the address in BAR2. The mapping of the bits in
this register are as follows:
The “WDT Timeout Select” field is used to select the timeout value of the Watchdog
Timer as follows:
The “SERR/RST Select” bit is used to select whether the WDT generates an SERR# on
the local PCI bus or a system reset. If this bit is set to “0”, the WDT will generate a
system reset. Otherwise, the WDT will make the local PCI bus SERR# signal active.
The “WDT Enable” bit is used to enable the Watchdog Timer function. This bit must
be set to “1” in order for the Watchdog Timer to function. Note that since all registers
default to zero after reset, the Watchdog Timer is always disabled after a reset. The
Watchdog Timer must be re-enabled by the application software after reset in order
for the Watchdog Timer to continue to operate. Once the Watchdog Timer is enabled,
the application software must refresh the Watchdog Timer within the selected timeout
period to prevent a reset or SERR# from being generated. The Watchdog Timer is
Field Bits Read or Write
SERR/RST Select WCSR[16] R/W
WDT Timeout Select WCSR[10..8] R/W
WDT Enable WCSR[0] R/W
All of these bits default to “0” after system reset. All other bits are reserved.
Timeout WCSR[10] WCSR[9] WCSR[8]
135s 0 0 0
33.6s 0 0 1
2.1s 0 1 0
524ms 0 1 1
262ms 1 0 0
131ms 1 0 1
32.768ms 1 1 0

2.048ms 1 1 1

The following table shows the register definitions for the VMIVME-7807/

VME-7807RC (offset from BAR0).
Please refer to Table 3-1, “PCI Configuration Space Registers,” on page 47 for more
information concerning BAR0.
Table 3-2 Register Definitions Offset From BAR0
Register Name Offset
VMECOMM 0x00
Bit Name Bit Definition
MEC_SEL 0 Master big-endian enable bit 1=Big Endian,
0=Little Endian bit
SEC_SEL 1 Slave Big-Endian enable bit 1=Big Endian,
0=Little Endian
ABLE 2 Auxiliary BERR logic enable bit
1=Aux. BERR enabled 0=Aux. BERR disabled
BTO 3 Bus error timer enabled 1=enabled, 0=disabled
BTOV [1:0] 5:4 Timeout value
00 - 16μs
01 - 64μs
10 -256μs
11 - 1.00ms
BERRI 6 BERR interrupt enable 1=Interrupt enabled
0=Interrupt disabled
BERRST 7 BERR status read/clear bit
1=Clear BERR status, 0=Do nothing
SFENA 8 Enables generation of VME SYSFAIL upon
WDT timeout
1= Enable SYSFAIL generation, 0=Disable
Unused 9 Not Used
BPENA 10 Endian conversion bypass bit
1=bypass, 0=Not bypassed
VBENA 11 VME enable bit (VBENA)
1 = enabled, 0 = disabled
Unused 31:12 Not Used
VBAM 0x04
VME_ADDR 5:0 Latched VME Address Modifier
Unused 31:6 Not Used
SEC_SEL 0x001
VBAR 0x08
VME_ADDR All Latched VME Address
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