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GE VMICPCI-7055RC-323100 PowerPC® CompactPCI® Single Board Computer

From: | Author:Wang | Time :2024-12-18 | 57 visit: | Share:

Timer 4 is 32-bits wide and obtains its load count from the Timer 4 Load Count

Register (TMRLCR4), located at offset 0x18 from the address in BAR2. The mapping

of bits in this register are as follows:

When this field is written, Timer 4 is loaded with the written value on the next rising

edge of the timer clock, regardless of whether the timer is enabled or disabled. The

value stored in this register is also automatically reloaded on terminal count (or

timeout) of the timer.

Timer 1 & 2 Current Count Register (TMRCCR12)

The current count of timers 1 & 2 may be read via the Timer 1 & 2 Current Count

Register (TMRCCR12), located at offset 0x20 from the address in BAR2. The mapping

of bits in this register are as follows:

When either field is read, the current count value is latched and returned. There are

two modes that determine how the count is latched depending on the setting of the

“Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2

register description for more information on these two modes.

Timer 3 Current Count Register (TMRCCR3)

The current count of Timer 3 may be read via the Timer 3 Current Count Register

(TMRCCR3), located at offset 0x24 from the address in BAR2. The mapping of bits in

this register are as follows:

Field Bits Read or Write

Timer 4 Load Count TMRLCR4[31..0] R/W

Field Bits Read or Write

Timer 2 Count TMRCCR12[31..16] R.O.

Timer 1 Count TMRCCR12[15..0] R.O.

When this field is read, the current count value is latched and returned. There are two

modes that determine how the count is latched depending on the setting of the “Read

Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2 register

description for more information on these two modes.

Timer 4 Current Count Register (TMRCCR4)

The current count of Timer 4 may be read via the Timer 4 Current Count Register

(TMRCCR4), located at offset 0x28 from the address in BAR2. The mapping of bits in

this register are as follows:

When this field is read, the current count value is latched and returned. There are two

modes that determine how the count is latched depending on the setting of the “Read

Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2 register

description for more information on these two modes.

Timer 1 IRQ Clear (T1IC)

The Timer 1 IRQ Clear (T1IC) register is used to clear an interrupt caused by Timer 1.

Writing to this register, located at offset 0x30 from the address in BAR2, causes the

interrupt from Timer 1 to be cleared. This can also be done by writing a “0” to the

appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1).

This register is write only and the data written is irrelevant.

Timer 2 IRQ Clear (T2IC)

The Timer 2 IRQ Clear (T2IC) register is used to clear an interrupt caused by Timer 2.

Writing to this register, located at offset 0x34 from the address in BAR2, causes the

interrupt from Timer 2 to be cleared. This can also be done by writing a “0” to the

appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1).

This register is write only and the data written is irrelevant.

Timer 3 IRQ Clear (T3IC)

The Timer 3 IRQ Clear (T3IC) register is used to clear an interrupt caused by Timer 3.

Writing to this register, located at offset 0x38 from the address in BAR2, causes the

interrupt from Timer 3 to be cleared. This can also be done by writing a “0” to the

appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1).

This register is write only and the data written is irrelevant.

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