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GE IS220PRTDH1A IS220PRTDH1B RTD Input: 8 RTDs

From: | Author:Wang | Time :2024-12-18 | 90 visit: | Share:

Table 3-8 TMRCCR12 Bit Mapping

Field Bits Read or Write

Timer 2 Count TMRCCR12[31..16] Read Only

Timer 1 Count TMRCCR12[15..0] Read Only

When either field is read, the current count value is latched and returned. There

are two modes that determine how the count is latched depending on the setting

of the “Read Latch Select” bit in the Control Status Register (TCSR2). See the

TCSR2 register description for more information on these two modes.

3.3.7 Timer 3 Current Count Register (TMRCCR3)

The current count of Timer 3 may be read via the Timer 3 Current Count Register

(TMRCCR3), located at offset 0x24 from the address in BAR2. The mapping of bits

in this register is shown in Table 3-9.

Table 3-9 TMRCCR3 Bit Mapping

Field Bits Read or Write

Timer 3 Count TMRCCR3[31..0] Read Only

When this field is read, the current count value is latched and returned. There are

two modes that determine how the count is latched depending on the setting of

the “Read Latch Select” bit in the Control Status Register (TCSR2). See the TCSR2

register description for more information on these two modes.

3.3.8 Timer 4 Current Count Register (TMRCCR4)

The current count of Timer 4 may be read via the Timer 4 Current Count Register

(TMRCCR4), located at offset 0x28 from the address in BAR2. The mapping of bits

in this register is shown in Table 3-10.

Table 3-10 TMRCCR4 Bit Mapping

Field Bits Read or Write

Timer 4 Count TMRCCR4[31..0] Read Only

When this field is read, the current count value is latched and returned. There are

two modes that determine how the count is latched depending on the setting of

the “Read Latch Select” bit in the Control Status Register (TCSR2). See the TCSR2

register description for more information on these two modes.

3.3.9 Timer 1 IRQ Clear (T1IC)

The Timer 1 IRQ Clear (T1IC) register is used to clear an interrupt caused by

Timer 1. Writing to this register, located at offset 0x30 from the address in BAR2,

causes the interrupt from Timer 1 to be cleared. This can also be done by writing a

“0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status

Register (TCSR1). This register is write only and the data written is irrelevant.

3.3.10 Timer 2 IRQ Clear (T2IC)

The Timer 2 IRQ Clear (T2IC) register is used to clear an interrupt caused by

Timer 2. Writing to this register, located at offset 0x34 from the address in BAR2,

causes the interrupt from Timer 2 to be cleared. This can also be done by writing a

“0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status

Register (TCSR1). This register is write only and the data written is irrelevant.

3.3.11 Timer 3 IRQ Clear (T3IC)

The Timer 3 IRQ Clear (T3IC) register is used to clear an interrupt caused by

Timer 3. Writing to this register, located at offset 0x38 from the address in BAR2,

causes the interrupt from Timer 3 to be cleared. This can also be done by writing a

“0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status

Register (TCSR1). This register is write only and the data written is irrelevant.

3.3.12 Timer 4 IRQ Clear (T4IC)

The Timer 4 IRQ Clear (T4IC) register is used to clear an interrupt caused by

Timer 4. Writing to this register, located at offset 0x3C from the address in BAR2,

causes the interrupt from Timer 4 to be cleared. This can also be done by writing a

“0” to the appropriate “Timer x Caused IRQ” field of the timer Control Status

Register (TCSR1). This register is write only and the data written is irrelevant.

3.4 Watchdog Timer

The V7768/V7769 provide a programmable Watchdog Timer (WDT) which can be

used to reset the system if software integrity fails.

3.4.1 WDT Control Status Register (WCSR)

The WDT is controlled and monitored by the WDT Control Status Register

(WCSR) which is located at offset 0x08 from the address in BAR2. The mapping of

the bits in this register is shown in Table 3-11.

Table 3-11 WCSR Bit Mapping

Field Bits Read or Write

SERR/RST Select WCSR[16] R/W

WDT Timeout Select WCSR[10..8] R/W

WDT Enable WCSR[0] R/W

All of these bits default to “0” after system reset. All other bits are reserved.

The “WDT Timeout Select” field is used to select the timeout value of the WDT as

shown in Table 3-12.

Table 3-12 Selecting Timeout Value of the WDT

Timeout WCSR[10] WCSR[9] WCSR[8]

135 s 0 0 0

33.6 s 0 0 1

2.1 s 0 1 0

524 ms 0 1 1

262 ms 1 0 0

131 ms 1 0 1

32.768 ms 1 1 0

2.048 ms 1 1 1

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