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Home >> GE >> GE IS220PSCAH1A IS220PSCAH1B Serial communication: 6 channels
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GE IS220PSCAH1A IS220PSCAH1B Serial communication: 6 channels

From: | Author:Wang | Time :2024-12-18 | 118 visit: | Share:

GE IS220PSCAH1A IS220PSCAH1B Serial communication: 6 channels

The “SERR/RST Select” bit is used to select whether the WDT generates an SERR#
on the local PCI bus or a system reset. If this bit is set to “0”, the WDT will
generate a system reset. Otherwise, the WDT will make the local PCI bus SERR#
signal active.
The “WDT Enable” bit is used to enable the Watchdog Timer function. This bit
must be set to “1” in order for the Watchdog Timer to function. Note that since all
registers default to zero after reset, the Watchdog Timer is always disabled after a
reset. The Watchdog Timer must be re-enabled by the application software after
reset in order for the Watchdog Timer to continue to operate. Once the Watchdog
Timer is enabled, the application software must refresh the Watchdog Timer
within the selected timeout period to prevent a reset or SERR# from being
generated. The Watchdog Timer is refreshed by performing a write to the WDT
Keepalive register (WKPA). The data written is irrelevant.
3.4.2 WDT Keepalive Register (WKPA)
When enabled, the Watchdog Timer is prevented from resetting the system by
writing to the WDT Keepalive Register (WKPA) located at offset 0x0C from the
address in BAR2 within the selected timeout period. The data written to this
location is irrelevant.
3.5 NVRAM
The V7768/V7769 provide 32 KByte of non-volatile RAM. This memory is mapped
in 32K of address space starting at the address in BAR1. This memory is available
at any time and supports byte, short word and long word accesses from the PCI
bus. The contents of this memory are retained when the power to the board is

removed.

Table 3-13 Register Definitions Offset from BAR0

Register and Offset Bit Name Bit Definition
VMECOMM
Offset 0x00
MEC_SEL 0 Master Big-Endian Enable bit
1=Big Endian, 0=Little Endian
SEC_SEL 1 Slave Big-Endian Enable bit
1=Big Endian, 0=Little Endian
ABLE 2 Auxiliary BERR Logic Enable bit
1=Aux. BERR Enabled, 0=Aux. BERR Disabled
BTO 3 Bus Error Timer Enabled
1=Enable, 0=Disabled
BTOV [1:0] 5:4 Timeout Value
00 - 16 μs
01 - 64 μs
10 - 256 μs
11 - 1.00 ms
BERRI 6 BERR Interrupt Enable
1=Interrupt Enabled, 0=Interrupt Disabled
BERRST 7 BERR Status Read/Clear bit R/WC
1=Clear BERR status, 0=Do nothing
SFENA 8 Enables generation of VME SYSFAIL upon WDT
timeout
1=Enable SYSFAIL generation, 0=Disable
Unused 9 Not Used
BPENA 10 Endian Conversion Bypass bit
1=bypass, 0=Not bypassed
VBENA 11 VME Enable bit (VBENA)
1=Enabled, 0=Disabled
Unused 21:12 Not Used
VBAM
0x04
VME_ADD 5:0 Latched VME Address Modifier
Unused 31:6 Not Used
SEC_SEL 0x001
VBAR
0x08
VME_ADDR All Latched VME Address
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