K-WANG
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EMERSON PMC422/FP Controller
EMERSON PMC422/FP Controller
The PMC422/FP provides a uniquely effective solution for integrating serial I/O requirements into a VMEbus or CompactPCI system. Implemented on a single PMC card, the PMC422/FP is fully compatible with the current generation of VMEbus and CPCI single board computers, as well as any special purpose processor that includes a PMC connector.
FEATURES
·Read/write burst operation
·Data transfer in byte, word, and double-word
·Four ports routed to the front utilizing RJ-45 connectors or eight ports routed to the front utilizing a 68-pin SCSI cable (06-260000x).
·PMC/PCI form factor
·Eight general purpose Inputs
SPECIFICATION
Asynchronous:Yes
Channels:8
Form Factor:PMC
Front I/O:Yes
Interface:RS232/422/485
Basic functions of the controller
Data buffering:
Since the rate of I/O devices is low while the rate of CPU and memory is high, a buffer must be set up in the controller. In the output, the buffer is used to store the data transmitted from the host at high speed, and then only at the rate of the I/O device will be transmitted to the I/O device buffer data; in the input, the buffer is used to store the data from the I/O device to send the data to receive a batch of data, and then the buffer in the high-speed data transmission to the host.
Error control:
The device controller also manages error detection of data sent from I/O devices. If an error is found in the transmission, the error detection code is usually set and reported to the CPU, which then cancels the transmitted data and transmits it again. This ensures the correctness of the data input.
Data exchange:
This refers to the realisation of data exchange between the CPU and the controller, and between the controller and the device. For the former, it is through the data bus, by the CPU in parallel to write data into the controller, or from the controller in parallel to read out the data; for the latter, it is the device will be the data input to the controller, or from the controller to the device. For this purpose, data registers shall be set up in the controller.
Status Description:
Identifies and reports the status of the device The controller shall note down the status of the device for the CPU to know. For example, the CPU can start the controller to read data from the device only when the device is in a transmit-ready state. For this purpose, a status register shall be set up in the controller with each bit therein reflecting a particular state of the device. When the CPU reads in the contents of this register, it can learn the state of the device.
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